Alex Porosanu e99d719359 arch/arm: add SEC JR0 offset ... Freescale PPC SoCs do not hard-code security engine's Job Ring 0 address, rather a define is used. This patch adds the same functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts) Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>		2016-05-18 08:51:46 -07:00
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arc	arc/cache: really do flush_dcache_all() even if IOC exists	2016-04-21 20:09:59 +03:00
arm	arch/arm: add SEC JR0 offset	2016-05-18 08:51:46 -07:00
avr32	Change my mailaddress	2016-05-02 18:37:09 -04:00
blackfin	configs: Re-sync almost all of cmd/Kconfig	2016-04-25 15:09:40 -04:00
m68k
microblaze
mips	Fix various typos, scattered over the code.	2016-05-05 21:39:26 -04:00
nds32
nios2
openrisc
powerpc	Fix various typos, scattered over the code.	2016-05-05 21:39:26 -04:00
sandbox
sh
sparc
x86	x86: Correct typo of Miao Yan's email address	2016-04-22 11:26:32 +08:00
.gitignore
Kconfig