Marek Behún de49bd0e73 phy: marvell: a3700: Set USB3 RX wait depending on ref clock ... According to specification, CFG_PM_RXDLOZ_WAIT should be set to 0x7 when reference clock is at 25 MHz. The specification (at least the version I have) does not mentoin the setting for 40 MHz reference clock, but Marvell's U-Boot sets 0xC in that case. Signed-off-by: Marek Behun <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>		2018-05-14 10:00:15 +02:00
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comphy.h	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
comphy_a3700.c	phy: marvell: a3700: Set USB3 RX wait depending on ref clock	2018-05-14 10:00:15 +02:00
comphy_a3700.h	phy: marvell: a3700: Access USB3 register indirectly on lane 2	2018-05-14 10:00:15 +02:00
comphy_core.c	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
comphy_cp110.c	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
comphy_hpipe.h	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
comphy_mux.c	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
Kconfig	drivers/phy: Add Marvell SerDes / PHY drivers used on Armada 3k	2016-09-27 17:29:53 +02:00
Makefile	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
sata.h	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
utmi_phy.h	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00