Stefan Agner da91cfed54 ARM: non-sec: flush code cacheline aligned ... Flush operations need to be cacheline aligned to take effect, make sure to flush always complete cachelines. This avoids messages such as: CACHE: Misaligned operation at range [00900000, 009004d9] Signed-off-by: Stefan Agner <stefan.agner@toradex.com> Tested-by: Fabio Estevam <fabio.estevam@nxp.com>		2016-08-12 09:22:15 -04:00
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arm11	arm: Move check_cache_range() into a common place	2016-07-14 18:33:09 -04:00
arm720t	ARM: ARM720t: remove empty asm/arch/hardware.h	2015-04-23 08:52:27 -04:00
arm920t	arm: Allow skipping of low-level init with I-cache on	2016-06-12 23:49:38 +02:00
arm926ejs	arm: Move check_cache_range() into a common place	2016-07-14 18:33:09 -04:00
arm946es	arm: Allow skipping of low-level init with I-cache on	2016-06-12 23:49:38 +02:00
arm1136	common: Pass the boot device into spl_boot_mode()	2016-06-26 20:17:22 +02:00
arm1176	ARM: start.S: fix typo	2016-02-29 14:49:35 -05:00
armv7	ARM: non-sec: flush code cacheline aligned	2016-08-12 09:22:15 -04:00
armv7m	stm32: Add SDRAM support for stm32f746 discovery board	2016-07-14 18:22:43 -04:00
armv8	armv8: mmu: Detect page table overflow in emergency pt creation	2016-08-05 20:55:18 -04:00
pxa	pxa: add support for D- and I- caches	2016-03-27 09:13:00 -04:00
sa1100	arm: Allow skipping of low-level init with I-cache on	2016-06-12 23:49:38 +02:00
Makefile	Various Makefiles: Add SPDX-License-Identifier tags	2015-11-10 09:19:52 -05:00
u-boot-spl.lds	spl: arm: Make sure to include all of the u_boot_list entries	2016-03-16 15:27:55 -04:00
u-boot.lds	ARM: Add secure section for initialized data	2016-07-15 15:54:58 +02:00