Jens Kuske d5ac6eef91 sunxi: Tune H3 DRAM PLL to improve lock time ... The H3 PLL5 used for DRAM barely manages to lock to the required frequency before DRAM controller starts, sometimes leading to wrong delay-line calibration results. This patch changes the PLL tuning parameters to the same values as boot0 used, which speeds up the locking and fixes the problem. Signed-off-by: Jens Kuske <jenskuske@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>		2016-08-26 16:58:37 +02:00
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asm	sunxi: Tune H3 DRAM PLL to improve lock time	2016-08-26 16:58:37 +02:00
debug	arm: debug: replace license blocks with SPDX	2014-10-26 22:22:09 +01:00