Siva Durga Prasad Paladugu 71723aaec5 fpga: zynq: Add delay after PCFG_PROG_B change ... There is delay needed after PCFG_PROGB change if AES key source is efuse. This fixes the issue of encrypted bitstream loading with AES efuse as key source. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>		2018-04-09 12:14:50 +02:00
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ACEX1K.c
altera.c
cyclon2.c
fpga.c	fpga: Simplify error path in fpga_add	2018-03-23 09:34:42 +01:00
ivm_core.c
Kconfig	arm: zynq: fpga: Added Kconfig support for CONFIG_FPGA_ZYNQPL	2018-02-28 13:00:25 -05:00
lattice.c
Makefile	arm: socfpga: Add FPGA driver support for Arria 10	2017-07-26 10:31:44 +02:00
socfpga.c	arm: socfpga: Enhance FPGA program write rbf data with size >= 4 bytes	2017-11-26 02:34:10 +01:00
socfpga_arria10.c	wait_bit: use wait_for_bit_le32 and remove wait_for_bit	2018-01-24 12:03:43 +05:30
socfpga_gen5.c	arm: socfpga: Restructure FPGA driver in the preparation to support A10	2017-07-26 10:31:44 +02:00
spartan2.c
spartan3.c
stratixII.c
stratixv.c
virtex2.c
xilinx.c	fpga: allow programming fpga from FIT image for all FPGA drivers	2017-12-14 16:09:39 +01:00
zynqmppl.c	fpga: zynqmp: Fix the nonsecure bitstream loading issue	2018-04-09 12:14:50 +02:00
zynqpl.c	fpga: zynq: Add delay after PCFG_PROG_B change	2018-04-09 12:14:50 +02:00