mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2026-03-01 17:36:03 +01:00
In warm reset conditions on OMAP36xx/AM/DM37xx the rom code incorrectly sets the DPLL4 clock input divider to /6.5 which is an invalid value unless the input clock is 13MHz. When a JTAG emulator is attached, a warm reset is necessary after the emulator gains control of the process. This results in a loss of serial output due to the invalid DPLL4 settings. This patch fixes the issue by resetting the DPLL4 clock input divider to /1 when the input clock is not 13MHz. AM/DM37x TRM section 3.5.3.3.3.2.1 specifies that the /6.5 setting is only used when the input clock is 13MHz. Signed-off-by: Matt Porter <mporter@ti.com> |
||
|---|---|---|
| .. | ||
| am33xx | ||
| exynos | ||
| highbank | ||
| imx-common | ||
| mx5 | ||
| mx6 | ||
| omap-common | ||
| omap3 | ||
| omap4 | ||
| omap5 | ||
| s5p-common | ||
| s5pc1xx | ||
| tegra2 | ||
| u8500 | ||
| cache_v7.c | ||
| config.mk | ||
| cpu.c | ||
| Makefile | ||
| start.S | ||
| syslib.c | ||