Rajesh Bhagat 554d33f3db ddr: fsl: set cdr1 first in case 0.9v VDD is enabled for some SoCs ... Sets DDR configuration parameter cdr1 before all other settings to support case 0.9v VDD is enabled for some SoCs Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>		2018-01-23 11:20:03 -08:00
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altera	arm: socfpga: Convert Altera DDR SDRAM driver to use Kconfig	2017-04-14 14:06:57 +02:00
fsl	ddr: fsl: set cdr1 first in case 0.9v VDD is enabled for some SoCs	2018-01-23 11:20:03 -08:00
marvell	ddr: marvell: update ddr controller init and freq	2018-01-19 16:30:29 +01:00
microchip	drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.	2016-02-01 22:14:01 +01:00
Kconfig	arm: socfpga: Convert Altera DDR SDRAM driver to use Kconfig	2017-04-14 14:06:57 +02:00