Keerthy 06d43c808d arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode ... While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver. Fix this to mark the regions as XN by default. Signed-off-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Tom Rini <trini@konsulko.com>		2016-11-13 15:54:36 -05:00
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asm	arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode	2016-11-13 15:54:36 -05:00
debug	arm: debug: replace license blocks with SPDX	2014-10-26 22:22:09 +01:00