mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2026-03-07 09:51:05 +01:00
cfc0877b85
Change-Id: I3e00ee6e54dadcae9c45bc157c6391e6f0dbda55 Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
171 lines
9.2 KiB
C
171 lines
9.2 KiB
C
/*
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* Copyright (c) 2022, The Linux Foundation. All rights reserved.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __QCA8084_IF_CTRL_H_
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#define __QCA8084_IF_CTRL_H_
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#define EPHY_CFG_OFFSET 0xC90F018
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#define EPHY_CFG_EPHY0_ADDR_BOFFSET 0
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#define EPHY_CFG_EPHY1_ADDR_BOFFSET 5
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#define EPHY_CFG_EPHY2_ADDR_BOFFSET 10
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#define EPHY_CFG_EPHY3_ADDR_BOFFSET 15
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#define SERDES_CFG_OFFSET 0xC90F014
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#define SERDES_CFG_S0_ADDR_BOFFSET 0
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#define SERDES_CFG_S1_ADDR_BOFFSET 5
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#define SERDES_CFG_S1_XPCS_ADDR_BOFFSET 10
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#define QCA8084_UNIPHY_SGMII_0 0
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#define QCA8084_UNIPHY_SGMII_1 1
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#define QCA8084_UNIPHY_XPCS 2
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/*UNIPHY MII registers*/
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#define QCA8084_UNIPHY_PLL_POWER_ON_AND_RESET 0
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/*UNIPHY MII register field*/
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#define QCA8084_UNIPHY_ANA_SOFT_RESET 0
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#define QCA8084_UNIPHY_ANA_SOFT_RELEASE 0x40
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/*UNIPHY MMD*/
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#define QCA8084_UNIPHY_MMD1 0x1
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#define QCA8084_UNIPHY_MMD3 0x3
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#define QCA8084_UNIPHY_MMD26 0x1a
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#define QCA8084_UNIPHY_MMD27 0x1b
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#define QCA8084_UNIPHY_MMD28 0x1c
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#define QCA8084_UNIPHY_MMD31 0x1f
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/*UNIPHY MMD1 registers*/
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#define QCA8084_UNIPHY_MMD1_CDA_CONTROL1 0x20
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#define QCA8084_UNIPHY_MMD1_CALIBRATION4 0x78
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#define QCA8084_UNIPHY_MMD1_BYPASS_TUNING_IPG 0x189
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#define QCA8084_UNIPHY_MMD1_MODE_CTRL 0x11b
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#define QCA8084_UNIPHY_MMD1_CHANNEL0_CFG 0x120
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#define QCA8084_UNIPHY_MMD1_GMII_DATAPASS_SEL 0x180
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#define QCA8084_UNIPHY_MMD1_USXGMII_RESET 0x18c
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/*UNIPHY MMD1 register field*/
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#define QCA8084_UNIPHY_MMD1_BYPASS_TUNING_IPG_EN 0x0fff
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#define QCA8084_UNIPHY_MMD1_XPCS_MODE 0x1000
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#define QCA8084_UNIPHY_MMD1_SGMII_MODE 0x400
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#define QCA8084_UNIPHY_MMD1_SGMII_PLUS_MODE 0x800
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#define QCA8084_UNIPHY_MMD1_1000BASE_X 0x0
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#define QCA8084_UNIPHY_MMD1_SGMII_PHY_MODE 0x10
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#define QCA8084_UNIPHY_MMD1_SGMII_MAC_MODE 0x20
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#define QCA8084_UNIPHY_MMD1_SGMII_MODE_CTRL_MASK 0x1f70
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#define QCA8084_UNIPHY_MMD1_CH0_FORCE_SPEED_MASK 0xe
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#define QCA8084_UNIPHY_MMD1_CH0_AUTONEG_ENABLE 0x0
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#define QCA8084_UNIPHY_MMD1_CH0_FORCE_ENABLE 0x8
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#define QCA8084_UNIPHY_MMD1_CH0_FORCE_SPEED_1G 0x4
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#define QCA8084_UNIPHY_MMD1_CH0_FORCE_SPEED_100M 0x2
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#define QCA8084_UNIPHY_MMD1_CH0_FORCE_SPEED_10M 0x0
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#define QCA8084_UNIPHY_MMD1_DATAPASS_MASK 0x1
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#define QCA8084_UNIPHY_MMD1_DATAPASS_USXGMII 0x1
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#define QCA8084_UNIPHY_MMD1_DATAPASS_SGMII 0x0
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#define QCA8084_UNIPHY_MMD1_CALIBRATION_DONE 0x80
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#define QCA8084_UNIPHY_MMD1_SGMII_FUNC_RESET 0x10
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#define QCA8084_UNIPHY_MMD1_SGMII_ADPT_RESET 0x800
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#define QCA8084_UNIPHY_MMD1_SSCG_ENABLE 0x8
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/*UNIPHY MMD3 registers*/
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#define QCA8084_UNIPHY_MMD3_PCS_CTRL2 0x7
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#define QCA8084_UNIPHY_MMD3_AN_LP_BASE_ABL2 0x14
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#define QCA8084_UNIPHY_MMD3_10GBASE_R_PCS_STATUS1 0x20
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#define QCA8084_UNIPHY_MMD3_DIG_CTRL1 0x8000
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#define QCA8084_UNIPHY_MMD3_EEE_MODE_CTRL 0x8006
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#define QCA8084_UNIPHY_MMD3_VR_RPCS_TPC 0x8007
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#define QCA8084_UNIPHY_MMD3_EEE_TX_TIMER 0x8008
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#define QCA8084_UNIPHY_MMD3_EEE_RX_TIMER 0x8009
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#define QCA8084_UNIPHY_MMD3_MII_AM_INTERVAL 0x800a
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#define QCA8084_UNIPHY_MMD3_EEE_MODE_CTRL1 0x800b
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/*UNIPHY MMD3 register field*/
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#define QCA8084_UNIPHY_MMD3_PCS_TYPE_10GBASE_R 0
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#define QCA8084_UNIPHY_MMD3_10GBASE_R_UP 0x1000
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#define QCA8084_UNIPHY_MMD3_USXGMII_EN 0x200
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#define QCA8084_UNIPHY_MMD3_QXGMII_EN 0x1400
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#define QCA8084_UNIPHY_MMD3_MII_AM_INTERVAL_VAL 0x6018
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#define QCA8084_UNIPHY_MMD3_XPCS_SOFT_RESET 0x8000
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#define QCA8084_UNIPHY_MMD3_XPCS_EEE_CAP 0x40
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#define QCA8084_UNIPHY_MMD3_EEE_RES_REGS 0x100
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#define QCA8084_UNIPHY_MMD3_EEE_SIGN_BIT_REGS 0x40
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#define QCA8084_UNIPHY_MMD3_EEE_EN 0x3
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#define QCA8084_UNIPHY_MMD3_EEE_TSL_REGS 0xa
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#define QCA8084_UNIPHY_MMD3_EEE_TLU_REGS 0xc0
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#define QCA8084_UNIPHY_MMD3_EEE_TWL_REGS 0x1600
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#define QCA8084_UNIPHY_MMD3_EEE_100US_REG_REGS 0xc8
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#define QCA8084_UNIPHY_MMD3_EEE_RWR_REG_REGS 0x1c00
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#define QCA8084_UNIPHY_MMD3_EEE_TRANS_LPI_MODE 0x1
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#define QCA8084_UNIPHY_MMD3_EEE_TRANS_RX_LPI_MODE 0x100
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#define QCA8084_UNIPHY_MMD3_USXG_FIFO_RESET 0x400
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/*UNIPHY MMD26 27 28 31 registers*/
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#define QCA8084_UNIPHY_MMD_MII_CTRL 0
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#define QCA8084_UNIPHY_MMD_MII_DIG_CTRL 0x8000
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#define QCA8084_UNIPHY_MMD_MII_AN_INT_MSK 0x8001
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#define QCA8084_UNIPHY_MMD_MII_ERR_SEL 0x8002
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#define QCA8084_UNIPHY_MMD_MII_XAUI_MODE_CTRL 0x8004
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/*UNIPHY MMD26 27 28 31 register field*/
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#define QCA8084_UNIPHY_MMD_AN_COMPLETE_INT 0x1
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#define QCA8084_UNIPHY_MMD_MII_4BITS_CTRL 0x0
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#define QCA8084_UNIPHY_MMD_TX_CONFIG_CTRL 0x8
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#define QCA8084_UNIPHY_MMD_MII_AN_ENABLE 0x1000
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#define QCA8084_UNIPHY_MMD_MII_AN_RESTART 0x200
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#define QCA8084_UNIPHY_MMD_MII_AN_COMPLETE_INT 0x1
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#define QCA8084_UNIPHY_MMD_USXG_FIFO_RESET 0x20
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#define QCA8084_UNIPHY_MMD_XPC_SPEED_MASK 0x2060
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#define QCA8084_UNIPHY_MMD_XPC_SPEED_2500 0x20
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#define QCA8084_UNIPHY_MMD_XPC_SPEED_1000 0x40
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#define QCA8084_UNIPHY_MMD_XPC_SPEED_100 0x2000
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#define QCA8084_UNIPHY_MMD_XPC_SPEED_10 0
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#define QCA8084_UNIPHY_MMD_TX_IPG_CHECK_DISABLE 0x1
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#define UNIPHY_CLK_RATE_25M 25000000
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#define UNIPHY_CLK_RATE_50M 50000000
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#define UNIPHY_CLK_RATE_125M 125000000
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#define UNIPHY_CLK_RATE_312M 312500000
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#define UNIPHY_DEFAULT_RATE UNIPHY_CLK_RATE_125M
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typedef enum {
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QCA8084_UNIPHY_MAC = QCA8084_UNIPHY_MMD1_SGMII_MAC_MODE,
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QCA8084_UNIPHY_PHY = QCA8084_UNIPHY_MMD1_SGMII_PHY_MODE,
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QCA8084_UNIPHY_SGMII = QCA8084_UNIPHY_MMD1_SGMII_MODE,
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QCA8084_UNIPHY_SGMII_PLUS = QCA8084_UNIPHY_MMD1_SGMII_PLUS_MODE,
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QCA8084_UNIPHY_UQXGMII = QCA8084_UNIPHY_MMD1_XPCS_MODE,
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} qca8084_uniphy_mode_t;
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typedef enum {
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QCA8084_INTERFACE_CLOCK_MAC_MODE = 0,
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QCA8084_INTERFACE_CLOCK_PHY_MODE = 1,
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} qca8084_clock_mode_t;
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typedef enum {
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QCA8084_MAC_MODE_RGMII = 0,
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QCA8084_MAC_MODE_GMII,
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QCA8084_MAC_MODE_MII,
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QCA8084_MAC_MODE_SGMII,
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QCA8084_MAC_MODE_FIBER,
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QCA8084_MAC_MODE_RMII,
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QCA8084_MAC_MODE_SGMII_PLUS,
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QCA8084_MAC_MODE_DEFAULT
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} qca8084_mac_mode_t;
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typedef struct {
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qca8084_mac_mode_t mac_mode;
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qca8084_clock_mode_t clock_mode;
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bool auto_neg;
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u32 force_speed;
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bool prbs_enable;
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bool rem_phy_lpbk;
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} mac_config_t;
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#endif
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