mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2026-03-07 01:40:49 +01:00
b8611c7623
Currently if CONFIG_QCA8084_PHY is enabled means, it will build all qca8084 functions required for both PHY & switch mode. But, some ipq devices might uses anyone of them. So, add configs to seperate the PHY & switch mode and define it in corresponding defconfig file as per the need. Also, some of the qca8084 functions will be used only for debug purpose, those functions are moved under the config QCA8084_DEBUG. Thereby, we can save some space in the u-boot. Change-Id: I7e5f53869629a0c7cbbb12daf04ed782c9693623 Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
665 lines
20 KiB
C
665 lines
20 KiB
C
/*
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* Copyright (c) 2022, The Linux Foundation. All rights reserved.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "ipq_phy.h"
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#include "ipq_qca8084.h"
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#include "ipq_qca8084_clk.h"
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#include "ipq_qca8084_interface_ctrl.h"
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#include <malloc.h>
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#ifdef DEBUG
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#define pr_debug(fmt, args...) printf(fmt, ##args);
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#else
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#define pr_debug(fmt, args...)
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#endif
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extern void qca8084_phy_reset(u32 phy_id);
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extern u16 qca8084_phy_reg_read(u32 phy_id, u32 reg_id);
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extern u16 qca8084_phy_reg_write(u32 phy_id, u32 reg_id, u16 value);
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extern u16 qca8084_phy_mmd_read(u32 phy_id, u16 mmd_num, u16 reg_id);
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extern u16 qca8084_phy_mmd_write(u32 phy_id, u16 mmd_num, u16 reg_id,
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u16 value);
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extern void qca8084_phy_modify_mmd(uint32_t phy_addr, uint32_t mmd_num,
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uint32_t mmd_reg, uint32_t mask, uint32_t value);
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extern void qca8084_phy_modify_mii(uint32_t phy_addr, uint32_t mii_reg,
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uint32_t mask, uint32_t value);
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extern uint32_t ipq_mii_read(uint32_t reg);
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extern void ipq_mii_write(uint32_t reg, uint32_t val);
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extern void ipq_mii_update(uint32_t reg, uint32_t mask, uint32_t val);
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extern void qca8084_port_clk_en_set(uint32_t qca8084_port_id, uint8_t mask,
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uint8_t enable);
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extern void qca8084_clk_assert(const char *clock_id);
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extern void qca8084_port_clk_reset(uint32_t qca8084_port_id, uint8_t mask);
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extern void qca8084_port_clk_rate_set(uint32_t qca8084_port_id, uint32_t rate);
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#ifdef CONFIG_QCA8084_PHY_MODE
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extern void qca8084_clk_deassert(const char *clock_id);
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#endif
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#ifdef CONFIG_QCA8084_SWT_MODE
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extern void qca8084_uniphy_raw_clock_set(qca8084_clk_parent_t uniphy_clk,
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uint64_t rate);
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#endif
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void qca8084_serdes_addr_get(uint32_t serdes_id, uint32_t *address)
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{
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uint32_t data = 0;
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data = ipq_mii_read(SERDES_CFG_OFFSET);
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switch(serdes_id)
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{
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case QCA8084_UNIPHY_SGMII_0:
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*address = (data >> SERDES_CFG_S0_ADDR_BOFFSET) & 0x1f;
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break;
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case QCA8084_UNIPHY_SGMII_1:
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*address = (data >> SERDES_CFG_S1_ADDR_BOFFSET) & 0x1f;
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break;
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case QCA8084_UNIPHY_XPCS:
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*address = (data >> SERDES_CFG_S1_XPCS_ADDR_BOFFSET) & 0x1f;
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break;
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default:
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pr_debug("Serdes id not matching\n");
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break;
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}
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}
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static void qca8084_uniphy_calibration(uint32_t uniphy_addr)
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{
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uint16_t uniphy_data = 0;
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uint32_t retries = 100, calibration_done = 0;
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/* wait calibration done to uniphy*/
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while (calibration_done != QCA8084_UNIPHY_MMD1_CALIBRATION_DONE) {
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mdelay(1);
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if (retries-- == 0)
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pr_debug("uniphy callibration time out!\n");
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uniphy_data = qca8084_phy_mmd_read(uniphy_addr, QCA8084_UNIPHY_MMD1,
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QCA8084_UNIPHY_MMD1_CALIBRATION4);
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calibration_done = (uniphy_data & QCA8084_UNIPHY_MMD1_CALIBRATION_DONE);
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}
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}
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void qca8084_port_speed_clock_set(uint32_t qca8084_port_id,
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fal_port_speed_t speed)
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{
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uint32_t clk_rate = 0;
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switch(speed)
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{
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case FAL_SPEED_2500:
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clk_rate = UQXGMII_SPEED_2500M_CLK;
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break;
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case FAL_SPEED_1000:
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clk_rate = UQXGMII_SPEED_1000M_CLK;
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break;
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case FAL_SPEED_100:
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clk_rate = UQXGMII_SPEED_100M_CLK;
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break;
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case FAL_SPEED_10:
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clk_rate = UQXGMII_SPEED_10M_CLK;
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break;
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default:
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pr_debug("Unknown speed\n");
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return;
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}
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qca8084_port_clk_rate_set(qca8084_port_id, clk_rate);
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}
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#ifdef CONFIG_QCA8084_PHY_MODE
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void qca8084_ephy_addr_get(uint32_t qca8084_port_id, uint32_t *phy_addr)
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{
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uint32_t data = 0;
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data = ipq_mii_read(EPHY_CFG_OFFSET);
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switch(qca8084_port_id)
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{
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case PORT1:
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*phy_addr = (data >> EPHY_CFG_EPHY0_ADDR_BOFFSET) & 0x1f;
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break;
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case PORT2:
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*phy_addr = (data >> EPHY_CFG_EPHY1_ADDR_BOFFSET) & 0x1f;
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break;
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case PORT3:
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*phy_addr = (data >> EPHY_CFG_EPHY2_ADDR_BOFFSET) & 0x1f;
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break;
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case PORT4:
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*phy_addr = (data >> EPHY_CFG_EPHY3_ADDR_BOFFSET) & 0x1f;
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break;
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default:
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pr_debug("qca8084_port_id not matching\n");
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break;
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}
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}
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static uint16_t qca8084_uniphy_xpcs_mmd_read(uint16_t mmd_num, uint16_t mmd_reg)
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{
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uint32_t uniphy_xpcs_addr = 0;
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qca8084_serdes_addr_get(QCA8084_UNIPHY_XPCS, &uniphy_xpcs_addr);
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return qca8084_phy_mmd_read(uniphy_xpcs_addr, mmd_num, mmd_reg);
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}
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static void qca8084_uniphy_xpcs_mmd_write(uint16_t mmd_num, uint16_t mmd_reg,
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uint16_t reg_val)
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{
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uint32_t uniphy_xpcs_addr = 0;
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#ifdef DEBUG
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uint16_t phy_data = 0;
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#endif
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qca8084_serdes_addr_get(QCA8084_UNIPHY_XPCS, &uniphy_xpcs_addr);
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qca8084_phy_mmd_write(uniphy_xpcs_addr, mmd_num, mmd_reg, reg_val);
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/*check the mmd register value*/
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#ifdef DEBUG
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phy_data =
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#endif
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qca8084_uniphy_xpcs_mmd_read(mmd_num, mmd_reg);
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pr_debug("phy_addr:0x%x, mmd_num:0x%x, mmd_reg:0x%x, phy_data:0x%x\n",
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uniphy_xpcs_addr, mmd_num, mmd_reg, phy_data);
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}
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static void qca8084_uniphy_xpcs_modify_mmd(uint32_t mmd_num, uint32_t mmd_reg,
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uint32_t mask, uint32_t value)
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{
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uint16_t phy_data = 0, new_phy_data = 0;
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phy_data = qca8084_uniphy_xpcs_mmd_read(mmd_num, mmd_reg);
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new_phy_data = (phy_data & ~mask) | value;
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qca8084_uniphy_xpcs_mmd_write(mmd_num, mmd_reg, new_phy_data);
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}
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uint8_t qca8084_uniphy_mode_check(uint32_t uniphy_index,
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qca8084_uniphy_mode_t uniphy_mode)
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{
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uint32_t uniphy_addr = 0;
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uint16_t uniphy_mode_ctrl_data = 0;
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qca8084_serdes_addr_get(uniphy_index, &uniphy_addr);
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uniphy_mode_ctrl_data = qca8084_phy_mmd_read(uniphy_addr,
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QCA8084_UNIPHY_MMD1, QCA8084_UNIPHY_MMD1_MODE_CTRL);
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if(uniphy_mode_ctrl_data == PHY_INVALID_DATA)
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return 0;
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if(!(uniphy_mode & uniphy_mode_ctrl_data))
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return 0;
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return 1;
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}
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static uint32_t qca8084_uniphy_xpcs_port_to_mmd(uint32_t qca8084_port_id)
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{
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uint32_t mmd_id = 0;
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switch(qca8084_port_id)
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{
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case PORT1:
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mmd_id = QCA8084_UNIPHY_MMD31;
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break;
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case PORT2:
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mmd_id = QCA8084_UNIPHY_MMD26;
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break;
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case PORT3:
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mmd_id = QCA8084_UNIPHY_MMD27;
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break;
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case PORT4:
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mmd_id = QCA8084_UNIPHY_MMD28;
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break;
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default:
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pr_debug("Port not matching qca8084 ports\n");
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}
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return mmd_id;
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}
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static void qca8084_uniphy_xpcs_modify_port_mmd(uint32_t qca8084_port_id,
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uint32_t mmd_reg, uint32_t mask,
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uint32_t value)
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{
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uint32_t mmd_id = 0;
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mmd_id = qca8084_uniphy_xpcs_port_to_mmd(qca8084_port_id);
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qca8084_uniphy_xpcs_modify_mmd(mmd_id, mmd_reg, mask, value);
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}
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static void qca8084_uniphy_xpcs_8023az_enable(void)
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{
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uint16_t uniphy_data = 0;
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uniphy_data = qca8084_uniphy_xpcs_mmd_read(QCA8084_UNIPHY_MMD3,
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QCA8084_UNIPHY_MMD3_AN_LP_BASE_ABL2);
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if(!(uniphy_data & QCA8084_UNIPHY_MMD3_XPCS_EEE_CAP))
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return;
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/*Configure the EEE related timer*/
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qca8084_uniphy_xpcs_modify_mmd(QCA8084_UNIPHY_MMD3,
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QCA8084_UNIPHY_MMD3_EEE_MODE_CTRL,
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0x0f40, QCA8084_UNIPHY_MMD3_EEE_RES_REGS |
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QCA8084_UNIPHY_MMD3_EEE_SIGN_BIT_REGS);
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qca8084_uniphy_xpcs_modify_mmd(QCA8084_UNIPHY_MMD3,
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QCA8084_UNIPHY_MMD3_EEE_TX_TIMER,
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0x1fff, QCA8084_UNIPHY_MMD3_EEE_TSL_REGS|
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QCA8084_UNIPHY_MMD3_EEE_TLU_REGS |
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QCA8084_UNIPHY_MMD3_EEE_TWL_REGS);
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qca8084_uniphy_xpcs_modify_mmd(QCA8084_UNIPHY_MMD3,
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QCA8084_UNIPHY_MMD3_EEE_RX_TIMER,
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0x1fff, QCA8084_UNIPHY_MMD3_EEE_100US_REG_REGS|
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QCA8084_UNIPHY_MMD3_EEE_RWR_REG_REGS);
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/*enable TRN_LPI*/
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qca8084_uniphy_xpcs_modify_mmd(QCA8084_UNIPHY_MMD3,
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QCA8084_UNIPHY_MMD3_EEE_MODE_CTRL1,
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0x101, QCA8084_UNIPHY_MMD3_EEE_TRANS_LPI_MODE|
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QCA8084_UNIPHY_MMD3_EEE_TRANS_RX_LPI_MODE);
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/*enable TX/RX LPI pattern*/
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qca8084_uniphy_xpcs_modify_mmd(QCA8084_UNIPHY_MMD3,
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QCA8084_UNIPHY_MMD3_EEE_MODE_CTRL,
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0x3, QCA8084_UNIPHY_MMD3_EEE_EN);
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}
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static void qca8084_uniphy_xpcs_10g_r_linkup(void)
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{
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uint16_t uniphy_data = 0;
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uint32_t retries = 100, linkup = 0;
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/* wait 10G_R link up */
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while (linkup != QCA8084_UNIPHY_MMD3_10GBASE_R_UP) {
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mdelay(1);
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if (retries-- == 0)
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pr_debug("10g_r link up timeout\n");
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uniphy_data = qca8084_uniphy_xpcs_mmd_read(QCA8084_UNIPHY_MMD3,
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QCA8084_UNIPHY_MMD3_10GBASE_R_PCS_STATUS1);
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linkup = (uniphy_data & QCA8084_UNIPHY_MMD3_10GBASE_R_UP);
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}
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}
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static void qca8084_uniphy_xpcs_soft_reset(void)
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{
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uint16_t uniphy_data = 0;
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uint32_t retries = 100, reset_done = QCA8084_UNIPHY_MMD3_XPCS_SOFT_RESET;
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qca8084_uniphy_xpcs_modify_mmd(QCA8084_UNIPHY_MMD3,
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QCA8084_UNIPHY_MMD3_DIG_CTRL1, 0x8000,
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QCA8084_UNIPHY_MMD3_XPCS_SOFT_RESET);
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while (reset_done) {
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mdelay(1);
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if (retries-- == 0)
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pr_debug("xpcs soft reset timeout\n");
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uniphy_data = qca8084_uniphy_xpcs_mmd_read(QCA8084_UNIPHY_MMD3,
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QCA8084_UNIPHY_MMD3_DIG_CTRL1);
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reset_done = (uniphy_data & QCA8084_UNIPHY_MMD3_XPCS_SOFT_RESET);
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}
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}
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void qca8084_uniphy_xpcs_speed_set(uint32_t qca8084_port_id,
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fal_port_speed_t speed)
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{
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uint32_t xpcs_speed = 0;
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switch(speed)
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{
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case FAL_SPEED_2500:
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xpcs_speed = QCA8084_UNIPHY_MMD_XPC_SPEED_2500;
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break;
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case FAL_SPEED_1000:
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xpcs_speed = QCA8084_UNIPHY_MMD_XPC_SPEED_1000;
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break;
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case FAL_SPEED_100:
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xpcs_speed = QCA8084_UNIPHY_MMD_XPC_SPEED_100;
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break;
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case FAL_SPEED_10:
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xpcs_speed = QCA8084_UNIPHY_MMD_XPC_SPEED_10;
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break;
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default:
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pr_debug("Unknown speed\n");
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return;
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}
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qca8084_uniphy_xpcs_modify_port_mmd(qca8084_port_id,
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QCA8084_UNIPHY_MMD_MII_CTRL,
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QCA8084_UNIPHY_MMD_XPC_SPEED_MASK,
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xpcs_speed);
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}
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void qca8084_uniphy_uqxgmii_function_reset(uint32_t qca8084_port_id)
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{
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uint32_t uniphy_addr = 0;
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qca8084_serdes_addr_get(QCA8084_UNIPHY_SGMII_1, &uniphy_addr);
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qca8084_phy_modify_mmd(uniphy_addr, QCA8084_UNIPHY_MMD1,
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QCA8084_UNIPHY_MMD1_USXGMII_RESET, BIT(qca8084_port_id-1), 0);
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mdelay(1);
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qca8084_phy_modify_mmd(uniphy_addr, QCA8084_UNIPHY_MMD1,
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QCA8084_UNIPHY_MMD1_USXGMII_RESET, BIT(qca8084_port_id-1),
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BIT(qca8084_port_id-1));
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if(qca8084_port_id == PORT1)
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qca8084_uniphy_xpcs_modify_mmd(QCA8084_UNIPHY_MMD3,
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QCA8084_UNIPHY_MMD_MII_DIG_CTRL,
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0x400, QCA8084_UNIPHY_MMD3_USXG_FIFO_RESET);
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else
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qca8084_uniphy_xpcs_modify_port_mmd(qca8084_port_id,
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QCA8084_UNIPHY_MMD_MII_DIG_CTRL,
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0x20, QCA8084_UNIPHY_MMD_USXG_FIFO_RESET);
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}
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void qca8084_uniphy_xpcs_autoneg_restart(uint32_t qca8084_port_id)
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{
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uint32_t retries = 500, uniphy_data = 0, mmd_id = 0;
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mmd_id = qca8084_uniphy_xpcs_port_to_mmd(qca8084_port_id);
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qca8084_uniphy_xpcs_modify_mmd(mmd_id, QCA8084_UNIPHY_MMD_MII_CTRL,
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QCA8084_UNIPHY_MMD_MII_AN_RESTART, QCA8084_UNIPHY_MMD_MII_AN_RESTART);
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mdelay(1);
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uniphy_data = qca8084_uniphy_xpcs_mmd_read(mmd_id,
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QCA8084_UNIPHY_MMD_MII_ERR_SEL);
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while(!(uniphy_data & QCA8084_UNIPHY_MMD_MII_AN_COMPLETE_INT))
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{
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mdelay(1);
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if (retries-- == 0)
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{
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pr_debug("xpcs uniphy autoneg restart timeout\n");
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}
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uniphy_data = qca8084_uniphy_xpcs_mmd_read(mmd_id,
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QCA8084_UNIPHY_MMD_MII_ERR_SEL);
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}
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}
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static void _qca8084_interface_uqxgmii_mode_set(uint32_t uniphy_addr)
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{
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uint32_t qca8084_port_id = 0, phy_addr = 0;
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/*reset xpcs*/
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pr_debug("reset xpcs\n");
|
|
qca8084_clk_assert(QCA8084_UNIPHY_XPCS_RST);
|
|
/*select xpcs mode*/
|
|
pr_debug("select xpcs mode\n");
|
|
qca8084_phy_modify_mmd(uniphy_addr, QCA8084_UNIPHY_MMD1,
|
|
QCA8084_UNIPHY_MMD1_MODE_CTRL, 0x1f00, QCA8084_UNIPHY_MMD1_XPCS_MODE);
|
|
/*config dapa pass as usxgmii*/
|
|
pr_debug("config dapa pass as usxgmii\n");
|
|
qca8084_phy_modify_mmd(uniphy_addr, QCA8084_UNIPHY_MMD1,
|
|
QCA8084_UNIPHY_MMD1_GMII_DATAPASS_SEL, QCA8084_UNIPHY_MMD1_DATAPASS_MASK,
|
|
QCA8084_UNIPHY_MMD1_DATAPASS_USXGMII);
|
|
/*reset and release uniphy GMII/XGMII and ethphy GMII*/
|
|
pr_debug("reset and release uniphy GMII/XGMII and ethphy GMII\n");
|
|
for(qca8084_port_id = PORT1; qca8084_port_id <= PORT4;
|
|
qca8084_port_id++)
|
|
{
|
|
qca8084_port_clk_reset(qca8084_port_id,
|
|
QCA8084_CLK_TYPE_UNIPHY|QCA8084_CLK_TYPE_EPHY);
|
|
}
|
|
|
|
/*ana sw reset and release*/
|
|
pr_debug("ana sw reset and release\n");
|
|
qca8084_phy_modify_mii(uniphy_addr,
|
|
QCA8084_UNIPHY_PLL_POWER_ON_AND_RESET, 0x40, QCA8084_UNIPHY_ANA_SOFT_RESET);
|
|
mdelay(10);
|
|
qca8084_phy_modify_mii(uniphy_addr,
|
|
QCA8084_UNIPHY_PLL_POWER_ON_AND_RESET, 0x40, QCA8084_UNIPHY_ANA_SOFT_RELEASE);
|
|
|
|
/*Wait calibration done*/
|
|
pr_debug("Wait calibration done\n");
|
|
qca8084_uniphy_calibration(uniphy_addr);
|
|
/*Enable SSCG(Spread Spectrum Clock Generator)*/
|
|
pr_debug("enable uniphy sscg\n");
|
|
qca8084_phy_modify_mmd(uniphy_addr, QCA8084_UNIPHY_MMD1,
|
|
QCA8084_UNIPHY_MMD1_CDA_CONTROL1, 0x8, QCA8084_UNIPHY_MMD1_SSCG_ENABLE);
|
|
/*release XPCS*/
|
|
pr_debug("release XPCS\n");
|
|
qca8084_clk_deassert(QCA8084_UNIPHY_XPCS_RST);
|
|
/*ethphy software reset*/
|
|
pr_debug("ethphy software reset\n");
|
|
for(qca8084_port_id = PORT1; qca8084_port_id <= PORT4;
|
|
qca8084_port_id++)
|
|
{
|
|
qca8084_ephy_addr_get(qca8084_port_id, &phy_addr);
|
|
qca8084_phy_reset(phy_addr);
|
|
}
|
|
/*Set BaseR mode*/
|
|
pr_debug("Set BaseR mode\n");
|
|
qca8084_uniphy_xpcs_modify_mmd(QCA8084_UNIPHY_MMD3,
|
|
QCA8084_UNIPHY_MMD3_PCS_CTRL2, 0xf, QCA8084_UNIPHY_MMD3_PCS_TYPE_10GBASE_R);
|
|
/*wait 10G base_r link up*/
|
|
pr_debug("wait 10G base_r link up\n");
|
|
qca8084_uniphy_xpcs_10g_r_linkup();
|
|
/*enable UQXGMII mode*/
|
|
pr_debug("enable UQSXGMII mode\n");
|
|
qca8084_uniphy_xpcs_modify_mmd(QCA8084_UNIPHY_MMD3,
|
|
QCA8084_UNIPHY_MMD3_DIG_CTRL1, 0x200, QCA8084_UNIPHY_MMD3_USXGMII_EN);
|
|
/*set UQXGMII mode*/
|
|
pr_debug("set QXGMII mode\n");
|
|
qca8084_uniphy_xpcs_modify_mmd(QCA8084_UNIPHY_MMD3,
|
|
QCA8084_UNIPHY_MMD3_VR_RPCS_TPC, 0x1c00, QCA8084_UNIPHY_MMD3_QXGMII_EN);
|
|
/*set AM interval*/
|
|
pr_debug("set AM interval\n");
|
|
qca8084_uniphy_xpcs_mmd_write(QCA8084_UNIPHY_MMD3,
|
|
QCA8084_UNIPHY_MMD3_MII_AM_INTERVAL, QCA8084_UNIPHY_MMD3_MII_AM_INTERVAL_VAL);
|
|
/*xpcs software reset*/
|
|
pr_debug("xpcs software reset\n");
|
|
qca8084_uniphy_xpcs_soft_reset();
|
|
}
|
|
|
|
void qca8084_interface_uqxgmii_mode_set(void)
|
|
{
|
|
uint32_t uniphy_addr = 0, qca8084_port_id = 0;
|
|
|
|
qca8084_serdes_addr_get(QCA8084_UNIPHY_SGMII_1, &uniphy_addr);
|
|
|
|
/*disable IPG_tuning bypass*/
|
|
pr_debug("disable IPG_tuning bypass\n");
|
|
qca8084_phy_modify_mmd(uniphy_addr, QCA8084_UNIPHY_MMD1,
|
|
QCA8084_UNIPHY_MMD1_BYPASS_TUNING_IPG,
|
|
QCA8084_UNIPHY_MMD1_BYPASS_TUNING_IPG_EN, 0);
|
|
/*disable uniphy GMII/XGMII clock and disable ethphy GMII clock*/
|
|
pr_debug("disable uniphy GMII/XGMII clock and ethphy GMII clock\n");
|
|
for(qca8084_port_id = PORT1; qca8084_port_id <= PORT4;
|
|
qca8084_port_id++)
|
|
{
|
|
qca8084_port_clk_en_set(qca8084_port_id,
|
|
QCA8084_CLK_TYPE_UNIPHY|QCA8084_CLK_TYPE_EPHY, 0);
|
|
}
|
|
/*configure uqxgmii mode*/
|
|
pr_debug("configure uqxgmii mode\n");
|
|
_qca8084_interface_uqxgmii_mode_set(uniphy_addr);
|
|
/*enable auto-neg complete interrupt,Mii using mii-4bits,
|
|
configure as PHY mode, enable autoneg ability*/
|
|
pr_debug("enable auto-neg complete interrupt, Mii using mii-4bits,"
|
|
" configure as PHY mode, enable autoneg ability, disable TICD\n");
|
|
for (qca8084_port_id = PORT1; qca8084_port_id <= PORT4;
|
|
qca8084_port_id++)
|
|
{
|
|
/*enable auto-neg complete interrupt,Mii using mii-4bits,configure as PHY mode*/
|
|
qca8084_uniphy_xpcs_modify_port_mmd(qca8084_port_id,
|
|
QCA8084_UNIPHY_MMD_MII_AN_INT_MSK, 0x109,
|
|
QCA8084_UNIPHY_MMD_AN_COMPLETE_INT |
|
|
QCA8084_UNIPHY_MMD_MII_4BITS_CTRL |
|
|
QCA8084_UNIPHY_MMD_TX_CONFIG_CTRL);
|
|
|
|
/*enable autoneg ability*/
|
|
qca8084_uniphy_xpcs_modify_port_mmd(qca8084_port_id,
|
|
QCA8084_UNIPHY_MMD_MII_CTRL, 0x3060, QCA8084_UNIPHY_MMD_MII_AN_ENABLE |
|
|
QCA8084_UNIPHY_MMD_XPC_SPEED_1000);
|
|
|
|
/*disable TICD*/
|
|
qca8084_uniphy_xpcs_modify_port_mmd(qca8084_port_id,
|
|
QCA8084_UNIPHY_MMD_MII_XAUI_MODE_CTRL, 0x1,
|
|
QCA8084_UNIPHY_MMD_TX_IPG_CHECK_DISABLE);
|
|
}
|
|
|
|
/*enable EEE for xpcs*/
|
|
pr_debug("enable EEE for xpcs\n");
|
|
qca8084_uniphy_xpcs_8023az_enable();
|
|
}
|
|
#endif /* CONFIG_QCA8084_PHY_MODE */
|
|
|
|
#ifdef CONFIG_QCA8084_SWT_MODE
|
|
void qca8084_uniphy_sgmii_function_reset(u32 uniphy_index)
|
|
{
|
|
u32 uniphy_addr = 0;
|
|
|
|
qca8084_serdes_addr_get(uniphy_index, &uniphy_addr);
|
|
|
|
/*sgmii channel0 adpt reset*/
|
|
qca8084_phy_modify_mmd(uniphy_addr, QCA8084_UNIPHY_MMD1,
|
|
QCA8084_UNIPHY_MMD1_CHANNEL0_CFG, QCA8084_UNIPHY_MMD1_SGMII_ADPT_RESET, 0);
|
|
mdelay(1);
|
|
qca8084_phy_modify_mmd(uniphy_addr, QCA8084_UNIPHY_MMD1,
|
|
QCA8084_UNIPHY_MMD1_CHANNEL0_CFG, QCA8084_UNIPHY_MMD1_SGMII_ADPT_RESET,
|
|
QCA8084_UNIPHY_MMD1_SGMII_ADPT_RESET);
|
|
/*ipg tune reset*/
|
|
qca8084_phy_modify_mmd(uniphy_addr, QCA8084_UNIPHY_MMD1,
|
|
QCA8084_UNIPHY_MMD1_USXGMII_RESET, QCA8084_UNIPHY_MMD1_SGMII_FUNC_RESET, 0);
|
|
mdelay(1);
|
|
qca8084_phy_modify_mmd(uniphy_addr, QCA8084_UNIPHY_MMD1,
|
|
QCA8084_UNIPHY_MMD1_USXGMII_RESET, QCA8084_UNIPHY_MMD1_SGMII_FUNC_RESET,
|
|
QCA8084_UNIPHY_MMD1_SGMII_FUNC_RESET);
|
|
|
|
}
|
|
|
|
void qca8084_interface_sgmii_mode_set(u32 uniphy_index, u32 qca8084_port_id, mac_config_t *config)
|
|
{
|
|
u32 uniphy_addr = 0, mode_ctrl = 0, speed_mode = 0;
|
|
u32 uniphy_port_id = 0, ethphy_clk_mask = 0;
|
|
u64 raw_clk = 0;
|
|
|
|
/*get the uniphy address*/
|
|
qca8084_serdes_addr_get(uniphy_index, &uniphy_addr);
|
|
|
|
if(config->mac_mode == QCA8084_MAC_MODE_SGMII)
|
|
{
|
|
mode_ctrl = QCA8084_UNIPHY_MMD1_SGMII_MODE;
|
|
raw_clk = UNIPHY_CLK_RATE_125M;
|
|
}
|
|
else
|
|
{
|
|
mode_ctrl = QCA8084_UNIPHY_MMD1_SGMII_PLUS_MODE;
|
|
raw_clk = UNIPHY_CLK_RATE_312M;
|
|
}
|
|
|
|
if(config->clock_mode == QCA8084_INTERFACE_CLOCK_MAC_MODE)
|
|
mode_ctrl |= QCA8084_UNIPHY_MMD1_SGMII_MAC_MODE;
|
|
else
|
|
{
|
|
mode_ctrl |= QCA8084_UNIPHY_MMD1_SGMII_PHY_MODE;
|
|
/*eththy clock should be accessed for phy mode*/
|
|
ethphy_clk_mask = QCA8084_CLK_TYPE_EPHY;
|
|
}
|
|
|
|
pr_debug("uniphy:%d,mode:%s,autoneg_en:%d,force_speed:%d,clk_mask:0x%x\n",
|
|
uniphy_index, (config->mac_mode == QCA8084_MAC_MODE_SGMII)?"sgmii":"sgmii plus",
|
|
config->auto_neg, config->force_speed,
|
|
ethphy_clk_mask);
|
|
|
|
/*GMII interface clock disable*/
|
|
pr_debug("GMII interface clock disable\n");
|
|
qca8084_port_clk_en_set(qca8084_port_id, ethphy_clk_mask, 0);
|
|
|
|
/*when access uniphy0 clock, port5 should be used, but for phy mode,
|
|
the port 4 connect to uniphy0, so need to change the port id*/
|
|
if(uniphy_index == QCA8084_UNIPHY_SGMII_0)
|
|
uniphy_port_id = PORT5;
|
|
else
|
|
uniphy_port_id = qca8084_port_id;
|
|
qca8084_port_clk_en_set(uniphy_port_id, QCA8084_CLK_TYPE_UNIPHY, 0);
|
|
|
|
/*uniphy1 xpcs reset, and configure raw clk*/
|
|
if(uniphy_index == QCA8084_UNIPHY_SGMII_1)
|
|
{
|
|
pr_debug("uniphy1 xpcs reset, confiugre raw clock as:%lld\n",
|
|
raw_clk);
|
|
qca8084_clk_assert(QCA8084_UNIPHY_XPCS_RST);
|
|
qca8084_uniphy_raw_clock_set(QCA8084_P_UNIPHY1_RX, raw_clk);
|
|
qca8084_uniphy_raw_clock_set(QCA8084_P_UNIPHY1_TX, raw_clk);
|
|
}
|
|
else
|
|
{
|
|
pr_debug("uniphy0 configure raw clock as %lld\n", raw_clk);
|
|
qca8084_uniphy_raw_clock_set(QCA8084_P_UNIPHY0_RX, raw_clk);
|
|
qca8084_uniphy_raw_clock_set(QCA8084_P_UNIPHY0_TX, raw_clk);
|
|
}
|
|
|
|
/*configure SGMII mode or SGMII+ mode*/
|
|
qca8084_phy_modify_mmd(uniphy_addr, QCA8084_UNIPHY_MMD1,
|
|
QCA8084_UNIPHY_MMD1_MODE_CTRL, QCA8084_UNIPHY_MMD1_SGMII_MODE_CTRL_MASK,
|
|
mode_ctrl);
|
|
|
|
/*GMII datapass selection, 0 is for SGMII, 1 is for USXGMII*/
|
|
qca8084_phy_modify_mmd(uniphy_addr, QCA8084_UNIPHY_MMD1,
|
|
QCA8084_UNIPHY_MMD1_GMII_DATAPASS_SEL, QCA8084_UNIPHY_MMD1_DATAPASS_MASK, QCA8084_UNIPHY_MMD1_DATAPASS_SGMII);
|
|
/*configue force or autoneg*/
|
|
if(!config->auto_neg)
|
|
{
|
|
qca8084_port_speed_clock_set(qca8084_port_id,
|
|
config->force_speed);
|
|
switch (config->force_speed)
|
|
{
|
|
case FAL_SPEED_10:
|
|
speed_mode = QCA8084_UNIPHY_MMD1_CH0_FORCE_ENABLE |
|
|
QCA8084_UNIPHY_MMD1_CH0_FORCE_SPEED_10M;
|
|
break;
|
|
case FAL_SPEED_100:
|
|
speed_mode = QCA8084_UNIPHY_MMD1_CH0_FORCE_ENABLE |
|
|
QCA8084_UNIPHY_MMD1_CH0_FORCE_SPEED_100M;
|
|
break;
|
|
case FAL_SPEED_1000:
|
|
case FAL_SPEED_2500:
|
|
speed_mode = QCA8084_UNIPHY_MMD1_CH0_FORCE_ENABLE |
|
|
QCA8084_UNIPHY_MMD1_CH0_FORCE_SPEED_1G;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
speed_mode = QCA8084_UNIPHY_MMD1_CH0_AUTONEG_ENABLE;
|
|
}
|
|
qca8084_phy_modify_mmd(uniphy_addr, QCA8084_UNIPHY_MMD1,
|
|
QCA8084_UNIPHY_MMD1_CHANNEL0_CFG, QCA8084_UNIPHY_MMD1_CH0_FORCE_SPEED_MASK, speed_mode);
|
|
|
|
/*GMII interface clock reset and release\n*/
|
|
pr_debug("GMII interface clock reset and release\n");
|
|
qca8084_port_clk_reset(qca8084_port_id, ethphy_clk_mask);
|
|
qca8084_port_clk_reset(uniphy_port_id, QCA8084_CLK_TYPE_UNIPHY);
|
|
|
|
/*analog software reset and release*/
|
|
pr_debug("analog software reset and release\n");
|
|
qca8084_phy_modify_mii(uniphy_addr,
|
|
QCA8084_UNIPHY_PLL_POWER_ON_AND_RESET, 0x40, QCA8084_UNIPHY_ANA_SOFT_RESET);
|
|
mdelay(1);
|
|
qca8084_phy_modify_mii(uniphy_addr,
|
|
QCA8084_UNIPHY_PLL_POWER_ON_AND_RESET, 0x40, QCA8084_UNIPHY_ANA_SOFT_RELEASE);
|
|
|
|
/*wait uniphy calibration done*/
|
|
pr_debug("wait uniphy calibration done\n");
|
|
qca8084_uniphy_calibration(uniphy_addr);
|
|
|
|
/*GMII interface clock enable*/
|
|
pr_debug("GMII interface clock enable\n");
|
|
qca8084_port_clk_en_set(qca8084_port_id, ethphy_clk_mask, 1);
|
|
qca8084_port_clk_en_set(uniphy_port_id, QCA8084_CLK_TYPE_UNIPHY, 1);
|
|
|
|
return;
|
|
}
|
|
#endif /* CONFIG_QCA8084_SWT_MODE */
|