mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
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498754d0eb
Change-Id: Ibc6517c39f0f9a24e18e62a6810b529b2d60afcf Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
89 lines
2.8 KiB
C
89 lines
2.8 KiB
C
/*
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* Copyright (c) 2017-2019, 2021, The Linux Foundation. All rights reserved.
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*
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* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#define PPE_UNIPHY_INSTANCE0 0
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#define PPE_UNIPHY_INSTANCE1 1
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#define GCC_UNIPHY_REG_INC 0x10
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#define PPE_UNIPHY_OFFSET_CALIB_4 0x1E0
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#define UNIPHY_CALIBRATION_DONE 0x1
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#define PPE_UNIPHY_BASE 0X07A00000
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#define PPE_UNIPHY_REG_INC 0x10000
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#define PPE_UNIPHY_MODE_CONTROL 0x46C
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#define UNIPHY_XPCS_MODE (1 << 12)
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#define UNIPHY_SG_PLUS_MODE (1 << 11)
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#define UNIPHY_SG_MODE (1 << 10)
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#define UNIPHY_CH0_PSGMII_QSGMII (1 << 9)
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#define UNIPHY_CH0_QSGMII_SGMII (1 << 8)
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#define UNIPHY_CH4_CH1_0_SGMII (1 << 2)
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#define UNIPHY_CH1_CH0_SGMII (1 << 1)
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#define UNIPHY_CH0_ATHR_CSCO_MODE_25M (1 << 0)
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#define UNIPHY_INSTANCE_LINK_DETECT 0x570
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#define UNIPHY_MISC2_REG_OFFSET 0x218
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#define UNIPHY_MISC2_REG_SGMII_MODE 0x30
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#define UNIPHY_MISC2_REG_SGMII_PLUS_MODE 0x50
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#define UNIPHY_MISC2_REG_VALUE 0x70
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#define UNIPHY_MISC_SOURCE_SELECTION_REG_OFFSET 0x21c
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#define UNIPHY_MISC_SRC_PHY_MODE 0xa882
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#define UNIPHY_DEC_CHANNEL_0_INPUT_OUTPUT_4 0x480
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#define UNIPHY_FORCE_SPEED_25M (1 << 3)
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#define UNIPHY_PLL_RESET_REG_OFFSET 0x780
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#define UNIPHY_PLL_RESET_REG_VALUE 0x02bf
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#define UNIPHY_PLL_RESET_REG_DEFAULT_VALUE 0x02ff
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#define SR_XS_PCS_KR_STS1_ADDRESS 0x30020
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#define UNIPHY_10GR_LINKUP 0x1
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#define VR_XS_PCS_DIG_CTRL1_ADDRESS 0x38000
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#define USXG_EN (1 << 9)
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#define USRA_RST (1 << 10)
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#define VR_MII_AN_CTRL_ADDRESS 0x1f8001
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#define MII_AN_INTR_EN (1 << 0)
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#define MII_CTRL (1 << 8)
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#define SR_MII_CTRL_ADDRESS 0x1f0000
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#define AN_ENABLE (1 << 12)
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#define SS5 (1 << 5)
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#define SS6 (1 << 6)
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#define SS13 (1 << 13)
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#define DUPLEX_MODE (1 << 8)
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#define VR_MII_AN_INTR_STS 0x1f8002
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#define CL37_ANCMPLT_INTR (1 << 0)
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enum uniphy_reset_type {
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UNIPHY0_SOFT_RESET = 0,
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UNIPHY0_XPCS_RESET,
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UNIPHY1_SOFT_RESET,
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UNIPHY1_XPCS_RESET,
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UNIPHY2_SOFT_RESET,
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UNIPHY2_XPCS_RESET,
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UNIPHY_RST_MAX
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};
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void ppe_uniphy_mode_set(uint32_t uniphy_index, uint32_t mode);
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void ppe_uniphy_usxgmii_port_reset(uint32_t uniphy_index);
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void ppe_uniphy_usxgmii_duplex_set(uint32_t uniphy_index, int duplex);
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void ppe_uniphy_usxgmii_speed_set(uint32_t uniphy_index, int speed);
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void ppe_uniphy_usxgmii_autoneg_completed(uint32_t uniphy_index);
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