mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2026-03-14 21:10:27 +01:00
428fc1d379
ipq40xx, ipq807x hardware share the qca8075 phy. So the qca8075 phy mdio, driver has been moved to common directory for use by both the hardware. Change-Id: Id6e9342438ffbdf8599860df6fbb39bba30429b3 Signed-off-by: Jaiganesh Narayanan <njaigane@codeaurora.org>
121 lines
2.6 KiB
C
121 lines
2.6 KiB
C
/*
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* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <phy.h>
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#include <asm/io.h>
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#include <errno.h>
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#include "ipq_mdio.h"
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struct ipq_mdio_data {
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struct mii_bus *bus;
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int phy_irq[PHY_MAX_ADDR];
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};
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static int ipq_mdio_wait_busy(void)
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{
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int i;
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u32 busy;
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for (i = 0; i < IPQ_MDIO_RETRY; i++) {
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udelay(IPQ_MDIO_DELAY);
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busy = readl(IPQ_MDIO_BASE +
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MDIO_CTRL_4_REG) &
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MDIO_CTRL_4_ACCESS_BUSY;
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if (!busy)
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return 0;
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udelay(IPQ_MDIO_DELAY);
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}
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printf("%s: MDIO operation timed out\n",
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__func__);
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return -ETIMEDOUT;
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}
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int ipq_mdio_write(int mii_id, int regnum, u16 value)
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{
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if (ipq_mdio_wait_busy())
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return -ETIMEDOUT;
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/* Issue the phy addreass and reg */
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writel((mii_id << 8 | regnum),
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IPQ_MDIO_BASE + MDIO_CTRL_1_REG);
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/* Issue a write data */
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writel(value, IPQ_MDIO_BASE + MDIO_CTRL_2_REG);
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/* Issue write command */
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writel((MDIO_CTRL_4_ACCESS_START |
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MDIO_CTRL_4_ACCESS_CODE_WRITE),
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(IPQ_MDIO_BASE + MDIO_CTRL_4_REG));
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/* Wait for write complete */
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if (ipq_mdio_wait_busy())
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return -ETIMEDOUT;
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return 0;
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}
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int ipq_mdio_read(int mii_id, int regnum, ushort *data)
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{
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u32 val;
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if (ipq_mdio_wait_busy())
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return -ETIMEDOUT;
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/* Issue the phy address and reg */
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writel((mii_id << 8) | regnum,
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IPQ_MDIO_BASE + MDIO_CTRL_1_REG);
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/* issue read command */
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writel((MDIO_CTRL_4_ACCESS_START |
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MDIO_CTRL_4_ACCESS_CODE_READ),
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(IPQ_MDIO_BASE + MDIO_CTRL_4_REG));
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if (ipq_mdio_wait_busy())
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return -ETIMEDOUT;
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/* Read data */
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val = readl(IPQ_MDIO_BASE + MDIO_CTRL_3_REG);
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if (data != NULL)
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*data = val;
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return val;
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}
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int ipq_phy_write(struct mii_dev *bus,
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int addr, int dev_addr,
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int regnum, ushort value)
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{
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return ipq_mdio_write(addr, regnum, value);
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}
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int ipq_phy_read(struct mii_dev *bus,
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int addr, int dev_addr, int regnum)
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{
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return ipq_mdio_read(addr, regnum, NULL);
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}
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int ipq_sw_mdio_init(const char *name)
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{
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struct mii_dev *bus = mdio_alloc();
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if(!bus) {
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printf("Failed to allocate IPQ MDIO bus\n");
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return -1;
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}
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bus->read = ipq_phy_read;
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bus->write = ipq_phy_write;
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bus->reset = NULL;
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sprintf(bus->name, name);
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return mdio_register(bus);
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}
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