mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
bce99ec378
Disabled the cache commands config CONFIG_CMD_CACHE. This changes removes the icache and dcache commands. Signed-off-by: Karthick Shanmugham <kartshan@codeaurora.org> Change-Id: I0cfd4df12e452a15861f0df7f4512234113d315a
429 lines
10 KiB
C
429 lines
10 KiB
C
/*
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* Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _IPQ5018_H
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#define _IPQ5018_H
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#ifndef DO_DEPS_ONLY
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#include <generated/asm-offsets.h>
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#endif
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#define CONFIG_IPQ5018
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#undef CONFIG_QCA_DISABLE_SCM
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#define CONFIG_SPI_FLASH_CYPRESS
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_SYS_CACHELINE_SIZE 64
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#define CONFIG_IPQ_NO_RELOC
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#define CONFIG_SYS_VSNPRINTF
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/*
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* Enable Early and Late init
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* This config needs for secondary boot and to set BADOFF5E
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* This config also need for spi-nor boot,
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* set size and offset of hlos and rootfs
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*/
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_BOARD_LATE_INIT
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#define CONFIG_IPQ5018_UART
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SYS_BOOTM_LEN 0x4000000
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#define CONFIG_ENV_SIZE_MAX (256 << 10) /* 256 KB */
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/*
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* PSCI Calls enable
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*/
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#define CONFIG_ARMV7_PSCI
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/*
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* Enable Flashwrite command
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*/
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#define CONFIG_CMD_FLASHWRITE
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/*
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* Enable Env overwrite support
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*/
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#define CONFIG_ENV_OVERWRITE
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/*
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* select serial console configuration
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*/
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_DEVICE_NULLDEV
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
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115200}
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#define CONFIG_SYS_CBSIZE (512 * 2) /* Console I/O Buffer Size */
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/*
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svc_sp --> --------------
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irq_sp --> | |
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fiq_sp --> | |
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bd --> | |
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gd --> | |
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pgt --> | |
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malloc --> | |
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text_base --> |------------|
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*/
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE -\
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CONFIG_SYS_MALLOC_LEN - CONFIG_ENV_SIZE -\
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GENERATED_BD_INFO_SIZE)
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define TLMM_BASE 0x01000000
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#define GPIO_CONFIG_ADDR(x) (TLMM_BASE + (x)*0x1000)
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#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE + 0x4 + (x)*0x1000)
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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#define CONFIG_SYS_TEXT_BASE 0x4A920000
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#define CONFIG_SYS_SDRAM_SIZE 0x10000000
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#define CONFIG_MAX_RAM_BANK_SIZE CONFIG_SYS_SDRAM_SIZE
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (64 << 20))
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#define QCA_KERNEL_START_ADDR CONFIG_SYS_SDRAM_BASE
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#define QCA_DRAM_KERNEL_SIZE CONFIG_SYS_SDRAM_SIZE
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#define QCA_BOOT_PARAMS_ADDR (QCA_KERNEL_START_ADDR + 0x100)
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#define CONFIG_OF_COMBINE 1
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#define CONFIG_QCA_SMEM_BASE 0x4AB00000
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#define CONFIG_IPQ_FDT_HIGH 0x4A400000
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#define CONFIG_ENV_IS_IN_SPI_FLASH 1
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#define CONFIG_ENV_SECT_SIZE (64 * 1024)
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#define CONFIG_QCA_UBOOT_OFFSET 0xA800000
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#define CONFIG_UBOOT_END_ADDR 0x4AA00000
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/*
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* IPQ_TFTP_MIN_ADDR: Starting address of Linux HLOS region.
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* CONFIG_TZ_END_ADDR: Ending address of Trust Zone and starting
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* address of WLAN Area.
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* TFTP file can only be written in Linux HLOS region and WLAN AREA.
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*/
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#define IPQ_TFTP_MIN_ADDR (CONFIG_SYS_SDRAM_BASE + (16 << 20))
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#define CONFIG_TZ_END_ADDR (CONFIG_SYS_SDRAM_BASE + (88 << 21))
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#define CONFIG_SYS_SDRAM_END ((long long)CONFIG_SYS_SDRAM_BASE + gd->ram_size)
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#ifndef __ASSEMBLY__
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#include <compiler.h>
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extern loff_t board_env_offset;
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extern loff_t board_env_range;
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extern loff_t board_env_size;
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#endif
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#define CONFIG_IPQ5018_ENV 1
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#define CONFIG_ENV_OFFSET board_env_offset
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#define CONFIG_ENV_SIZE CONFIG_ENV_SIZE_MAX
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#define CONFIG_ENV_RANGE board_env_range
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE_MAX + (500 << 10))
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/*
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* NAND Flash Configs
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*/
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/* CONFIG_QPIC_NAND: QPIC NAND in BAM mode
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* CONFIG_IPQ_NAND: QPIC NAND in FIFO/block mode.
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* BAM is enabled by default.
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*/
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_SYS_NAND_SELF_INIT
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#ifdef CONFIG_NAND_FLASH
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#define CONFIG_CMD_NAND
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#define CONFIG_ENV_IS_IN_NAND 1
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#define CONFIG_QPIC_NAND
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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#define CONFIG_CMD_NAND_YAFFS
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#define CONFIG_MTD_DEVICE
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#define CONFIG_MTD_PARTITIONS
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#endif
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#ifdef CONFIG_QPIC_SERIAL
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#ifdef QSPI_SERIAL_DEBUG /* QSPI DEBUG */
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#define qspi_debug(fmt,args...) printf (fmt ,##args)
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#else
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#define qspi_debug(fmt,args...)
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#endif /* QSPI DEBUG */
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#define CONFIG_PAGE_SCOPE_MULTI_PAGE_READ
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#define CONFIG_QSPI_SERIAL_TRAINING
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#endif
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/*
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* SPI Flash Configs
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*/
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#define CONFIG_QCA_SPI
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#define CONFIG_SPI_FLASH
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#define CONFIG_CMD_SF
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#define CONFIG_SPI_FLASH_STMICRO
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#define CONFIG_SPI_FLASH_WINBOND
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#define CONFIG_SPI_FLASH_MACRONIX
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#define CONFIG_SPI_FLASH_GIGADEVICE
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#define CONFIG_SPI_FLASH_SPANSION
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#define CONFIG_SF_DEFAULT_BUS 0
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#define CONFIG_SF_DEFAULT_CS 0
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
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#define CONFIG_SF_DEFAULT_SPEED (48 * 1000 * 1000)
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#define CONFIG_SPI_FLASH_BAR 1
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#define CONFIG_SPI_FLASH_USE_4K_SECTORS
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#define CONFIG_IPQ_4B_ADDR_SWITCH_REQD
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#define CONFIG_QUP_SPI_USE_DMA 1
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#define CONFIG_QCA_BAM 1
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/*
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* MMC configs
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*/
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#ifdef CONFIG_MMC_FLASH
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#define CONFIG_QCA_MMC
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#define CONFIG_MMC
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#define CONFIG_CMD_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_SDHCI
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#define CONFIG_SDHCI_QCA
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#define CONFIG_ENV_IS_IN_MMC
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_SDHCI_SUPPORT
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#define CONFIG_MMC_ADMA
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#define CONFIG_EFI_PARTITION
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/*
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* eMMC controller support only 4-bit
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* force SDHC driver to 4-bit mode
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*/
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#define CONFIG_MMC_FORCE_CAP_4BIT_BUSWIDTH
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#endif
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/*
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* I2C Enable
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*/
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#ifdef CONFIG_IPQ5018_I2C
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#define CONFIG_SYS_I2C_QUP
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#define CONFIG_CMD_I2C
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#define CONFIG_DM_I2C
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#endif
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/*
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* GMAC Enable
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*/
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#define CONFIG_IPQ5018_GMAC
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#define CONFIG_IPQ5018_MDIO
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#define CONFIG_NET_RETRY_COUNT 5
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#define CONFIG_SYS_RX_ETH_BUFFER 16
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_MII
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#define CONFIG_IPADDR 192.168.10.10
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_SERVERIP 192.168.10.19
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#define CONFIG_CMD_TFTPPUT
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#define CONFIG_IPQ_MDIO 1
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#define CONFIG_IPQ_ETH_INIT_DEFER
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#define CONFIG_IPQ_NO_MACS 2
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/*
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* GEPHY
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*/
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#define CONFIG_GEPHY
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/*
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* USB Support
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*/
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#ifdef CONFIG_USB_XHCI_IPQ
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#define CONFIG_USB_XHCI
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#define CONFIG_USB_XHCI_DWC3
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#define CONFIG_CMD_USB
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#define CONFIG_USB_STORAGE
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#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
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/*
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* USB crashdump collection
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*/
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#define CONFIG_FS_FAT
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#define CONFIG_FAT_WRITE
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#define CONFIG_CMD_FAT
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/*
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* Block Device & Disk Partition Config
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*/
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#define HAVE_BLOCK_DEVICE
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#define CONFIG_DOS_PARTITION
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#endif
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/*
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* PCIE Enable
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*/
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#define PCI_MAX_DEVICES 2
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#if defined(CONFIG_PCI_IPQ)
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#define CONFIG_PCI
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#define CONFIG_CMD_PCI
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#define CONFIG_PCI_SCAN_SHOW
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#endif
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/*
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* Expose SPI driver as a pseudo NAND driver to make use
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* of U-Boot's MTD framework.
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*/
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#define CONFIG_SYS_MAX_NAND_DEVICE CONFIG_IPQ_MAX_NAND_DEVICE + \
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CONFIG_IPQ_MAX_SPI_DEVICE
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#define CONFIG_IPQ_MAX_NAND_DEVICE 1
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#define CONFIG_IPQ_MAX_SPI_DEVICE 1
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#define CONFIG_QPIC_NAND_NAND_INFO_IDX 0
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#define CONFIG_IPQ_SPI_NOR_INFO_IDX 1
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#define CONFIG_NAND_FLASH_INFO_IDX CONFIG_QPIC_NAND_NAND_INFO_IDX
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#define CONFIG_SPI_FLASH_INFO_IDX CONFIG_IPQ_SPI_NOR_INFO_IDX
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#define QCA_SPI_NOR_DEVICE "spi0.0"
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/*
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* U-Boot Env Configs
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*/
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_CMD_XIMG
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/* MTEST */
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x1300000
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#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + 0x100
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/* NSS firmware loaded using bootm */
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#define CONFIG_BOOTCOMMAND "bootipq"
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#define CONFIG_BOOTARGS "console=ttyMSM0,115200n8"
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#define QCA_ROOT_FS_PART_NAME "rootfs"
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#define CONFIG_BOOTDELAY 5
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#define NUM_ALT_PARTITION 16
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#ifdef CONFIG_IPQ_TINY
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/* undef gzip lib */
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#undef CONFIG_GZIP
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#undef CONFIG_ZLIB
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#else
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#define CONFIG_CMD_BOOTZ
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/* Multicore CPU support */
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#define CONFIG_SMP_CMD_SUPPORT
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/* Mii command support */
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#define CONFIG_CMD_MII
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/* compress crash dump support */
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#define CONFIG_CMD_ZIP
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#define CONFIG_GZIP_COMPRESSED
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/* Enable DTB compress */
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#define CONFIG_COMPRESSED_DTB_MAX_SIZE 0x40000
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#define CONFIG_COMPRESSED_DTB_BASE CONFIG_SYS_TEXT_BASE -\
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CONFIG_COMPRESSED_DTB_MAX_SIZE
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#endif
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#define CONFIG_FDT_FIXUP_PARTITIONS
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#define CONFIG_IPQ_FDT_FIXUP
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/*
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* Below Configs need to be updated after enabling reset_crashdump
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* Included now to avoid build failure
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*/
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#define CONFIG_OF_BOARD_SETUP
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#ifdef CONFIG_OF_BOARD_SETUP
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#define DLOAD_DISABLE 0x1
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#define SET_MAGIC 0x1
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#define CLEAR_MAGIC 0x0
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#define SCM_CMD_TZ_CONFIG_HW_FOR_RAM_DUMP_ID 0x9
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#define SCM_CMD_TZ_FORCE_DLOAD_ID 0x10
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#define SCM_CMD_TZ_PSHOLD 0x16
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#define BOOT_VERSION 0
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#define TZ_VERSION 1
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#endif
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#define CONFIG_IPQ5018_TZ_WONCE_4_ADDR 0x193d010
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/*
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* CRASH DUMP ENABLE
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*/
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#define CONFIG_QCA_APPSBL_DLOAD
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#define CONFIG_IPQ5018_DMAGIC_ADDR 0x193D100
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#ifdef CONFIG_QCA_APPSBL_DLOAD
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#undef CONFIG_NET_RETRY_COUNT
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#define CONFIG_NET_RETRY_COUNT 500
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#define IPQ_TEMP_DUMP_ADDR 0x44000000
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#endif
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#define CONFIG_QCA_KERNEL_CRASHDUMP_ADDRESS *((unsigned int *)0x08600658)
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#define CONFIG_CPU_CONTEXT_DUMP_SIZE 4096
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#define TLV_BUF_OFFSET 1012 * 1024
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#define CONFIG_TLV_DUMP_SIZE 12 * 1024
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/* L1 cache line size is 64 bytes, L2 cache line size is 128 bytes
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* Cache flush and invalidation based on L1 cache, so the cache line
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* size is configured to 64 */
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#define CONFIG_SYS_CACHELINE_SIZE 64
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/*
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* UBI write command
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*/
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#ifdef CONFIG_UBI_WRITE
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#define CONFIG_CMD_UBI
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#define CONFIG_RBTREE
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#define IPQ_UBI_VOL_WRITE_SUPPORT
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#endif
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#undef CONFIG_BOOTM_NETBSD
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#undef CONFIG_BOOTM_PLAN9
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#undef CONFIG_BOOTM_RTEMS
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#undef CONFIG_BOOTM_VXWORKS
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#ifdef CONFIG_ART_COMPRESSED
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/*
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* This location use to keep comprssed data for
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* uncompress process.
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* default location is CONFIG_SYS_LOAD_ADDR if not defined.
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*/
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#define CONFIG_COMPRESSED_LOAD_ADDR (CONFIG_SYS_LOAD_ADDR + (1 << 22))
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#endif
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#ifdef CONFIG_SMP_CMD_SUPPORT
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#define NR_CPUS 2
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#endif
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/*
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* 96 MHz
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*/
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#define INTERNAL_96MHZ
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/*#define CONFIG_IPQ_BT_SUPPORT*/
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#endif /* _IPQ5018_H */
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