mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
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0f0ae124bb
MDIO clock divider is set to 0x7 (counts to 8) to produce 12.5MHz (100MHz/8) MDC frequency. Change-Id: Ic7969aebf9fcbb14601ba8e56563959ab0b25657 Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
37 lines
1.3 KiB
C
37 lines
1.3 KiB
C
/*
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* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _IPQ_MDIO_H
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#define _IPQ_MDIO_H
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#define IPQ_MDIO_BASE 0x90000
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#define MDIO_CTRL_0_REG 0x40
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#define MDIO_CTRL_1_REG 0x44
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#define MDIO_CTRL_2_REG 0x48
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#define MDIO_CTRL_3_REG 0x4c
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#define MDIO_CTRL_4_REG 0x50
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#define MDIO_CTRL_4_ACCESS_BUSY (1 << 16)
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#define MDIO_CTRL_4_ACCESS_START (1 << 8)
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#define MDIO_CTRL_4_ACCESS_CODE_READ 0
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#define MDIO_CTRL_4_ACCESS_CODE_WRITE 1
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#define MDIO_CTRL_4_ACCESS_CODE_C45_ADDR 0
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#define MDIO_CTRL_4_ACCESS_CODE_C45_WRITE 1
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#define MDIO_CTRL_4_ACCESS_CODE_C45_READ 2
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#define CTRL_0_REG_DEFAULT_VALUE 0x1500F
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#ifdef MDIO_12_5_MHZ
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#define CTRL_0_REG_C45_DEFAULT_VALUE 0x15107
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#else
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#define CTRL_0_REG_C45_DEFAULT_VALUE 0x1510F
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#endif
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#define IPQ_MDIO_RETRY 1000
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#define IPQ_MDIO_DELAY 5
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#endif /* End _IPQ_MDIO_H */
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