mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
f9bf44c614
Change-Id: Ia2fc764ed69f5304d9837e39896d58820f073599 Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
251 lines
8.3 KiB
C
251 lines
8.3 KiB
C
/*
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**************************************************************************
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* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
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* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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**************************************************************************
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*/
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#include <common.h>
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#include <net.h>
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#include <asm-generic/errno.h>
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#include <asm/io.h>
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#include <malloc.h>
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#include <phy.h>
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#include <net.h>
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#include <miiphy.h>
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#define GCC_NSS_PORT1_RX_CMD_RCGR 0x01868020
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#define GCC_NSS_PORT1_RX_CFG_RCGR 0x01868024
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#define GCC_NSS_PORT1_RX_MISC 0x01868400
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#define IPQ807X_PPE_BASE_ADDR 0x3a000000
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#define IPQ807X_PPE_REG_SIZE 0x1000000
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#define PORT5 5
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#define PORT6 6
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#define PORT_GMAC_TYPE 1
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#define PORT_XGMAC_TYPE 2
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struct port_mux_ctrl {
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uint32_t port4_pcs_sel:1;
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uint32_t port5_pcs_sel:2;
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uint32_t port5_gmac_sel:1;
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uint32_t port6_pcs_sel:1;
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uint32_t port6_gmac_sel:1;
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uint32_t _reserved0:26;
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};
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union port_mux_ctrl_u {
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uint32_t val;
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struct port_mux_ctrl bf;
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};
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enum {
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TCP_PKT,
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UDP_PKT,
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};
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#define ADPT_ACL_HPPE_IPV4_DIP_RULE 4
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#define MAX_RULE 512
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struct ipo_rule_reg {
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uint32_t rule_field_0:32;
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uint32_t rule_field_1:20;
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uint32_t fake_mac_header:1;
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uint32_t range_en:1;
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uint32_t inverse_en:1;
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uint32_t rule_type:4;
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uint32_t src_type:2;
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uint32_t src_0:3;
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uint32_t src_1:5;
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uint32_t pri:9;
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uint32_t res_chain:1;
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uint32_t post_routing_en:1;
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uint32_t _reserved0:16;
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};
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union ipo_rule_reg_u {
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uint32_t val[3];
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struct ipo_rule_reg bf;
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};
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struct ipo_mask_reg {
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uint32_t maskfield_0:32;
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uint32_t maskfield_1:21;
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uint32_t _reserved0:11;
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};
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union ipo_mask_reg_u {
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uint32_t val[2];
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struct ipo_mask_reg bf;
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};
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struct ipo_action {
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uint32_t dest_info_change_en:1;
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uint32_t fwd_cmd:2;
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uint32_t _reserved0:29;
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uint32_t _reserved1:32;
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uint32_t _reserved2:32;
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uint32_t _reserved3:32;
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uint32_t _reserved4:32;
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};
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union ipo_action_u {
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uint32_t val[5];
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struct ipo_action bf;
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};
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#define IPQ807X_PORT_MUX_CTRL 0x10
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#define PORT4_PCS_SEL_GMII_FROM_PCS0 1
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#define PORT4_PCS_SEL_RGMII 0
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#define PORT5_PCS_SEL_RGMII 0
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#define PORT5_PCS_SEL_GMII_FROM_PCS0 1
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#define PORT5_PCS_SEL_GMII_FROM_PCS1 2
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#define PORT5_GMAC_SEL_GMAC 1
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#define PORT5_GMAC_SEL_XGMAC 0
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#define PORT6_PCS_SEL_RGMII 0
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#define PORT6_PCS_SEL_GMII_FROM_PCS2 1
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#define PORT6_GMAC_SEL_GMAC 1
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#define PORT6_GMAC_SEL_XGMAC 0
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#define PORT_PHY_STATUS_ADDRESS 0x44
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#define PORT_PHY_STATUS_PORT5_1_OFFSET 8
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#define PORT_PHY_STATUS_PORT6_OFFSET 16
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#define IPQ807X_PPE_IPE_L3_BASE_ADDR 0x200000
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#define IPQ807X_PPE_L3_VP_PORT_TBL_ADDR (IPQ807X_PPE_IPE_L3_BASE_ADDR + 0x1000)
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#define IPQ807X_PPE_L3_VP_PORT_TBL_INC 0x10
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#define IPQ807X_PPE_QUEUE_MANAGER_BASE_ADDR 0x800000
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#define IPQ807X_PPE_UCAST_QUEUE_MAP_TBL_ADDR 0x10000
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#define IPQ807X_PPE_UCAST_QUEUE_MAP_TBL_INC 0x10
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#define IPQ807X_PPE_QM_UQM_TBL (IPQ807X_PPE_QUEUE_MANAGER_BASE_ADDR +\
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IPQ807X_PPE_UCAST_QUEUE_MAP_TBL_ADDR)
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#define IPQ807X_PPE_UCAST_PRIORITY_MAP_TBL_ADDR 0x42000
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#define IPQ807X_PPE_QM_UPM_TBL (IPQ807X_PPE_QUEUE_MANAGER_BASE_ADDR +\
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IPQ807X_PPE_UCAST_PRIORITY_MAP_TBL_ADDR)
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#define IPQ807X_PPE_STP_BASE 0x060100
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#define IPQ807X_PPE_MAC_ENABLE 0x001000
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#define IPQ807X_PPE_MAC_SPEED 0x001004
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#define IPQ807X_PPE_MAC_MIB_CTL 0x001034
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#define IPQ807X_PPE_TRAFFIC_MANAGER_BASE_ADDR 0x400000
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#define IPQ807X_PPE_L0_FLOW_PORT_MAP_TBL_ADDR 0x8000
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#define IPQ807X_PPE_L0_FLOW_PORT_MAP_TBL_INC 0x10
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#define IPQ807X_PPE_L0_FLOW_PORT_MAP_TBL (IPQ807X_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
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IPQ807X_PPE_L0_FLOW_PORT_MAP_TBL_ADDR)
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#define IPQ807X_PPE_L0_FLOW_MAP_TBL_ADDR 0x2000
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#define IPQ807X_PPE_L0_FLOW_MAP_TBL_INC 0x10
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#define IPQ807X_PPE_L0_FLOW_MAP_TBL (IPQ807X_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
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IPQ807X_PPE_L0_FLOW_MAP_TBL_ADDR)
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#define IPQ807X_PPE_L1_FLOW_PORT_MAP_TBL_ADDR 0x46000
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#define IPQ807X_PPE_L1_FLOW_PORT_MAP_TBL_INC 0x10
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#define IPQ807X_PPE_L1_FLOW_PORT_MAP_TBL (IPQ807X_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
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IPQ807X_PPE_L1_FLOW_PORT_MAP_TBL_ADDR)
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#define IPQ807X_PPE_L1_FLOW_MAP_TBL_ADDR 0x40000
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#define IPQ807X_PPE_L1_FLOW_MAP_TBL_INC 0x10
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#define IPQ807X_PPE_L1_FLOW_MAP_TBL (IPQ807X_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
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IPQ807X_PPE_L1_FLOW_MAP_TBL_ADDR)
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#define IPQ807X_PPE_L0_C_SP_CFG_TBL_ADDR 0x4000
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#define IPQ807X_PPE_L0_C_SP_CFG_TBL (IPQ807X_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
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IPQ807X_PPE_L0_C_SP_CFG_TBL_ADDR)
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#define IPQ807X_PPE_L1_C_SP_CFG_TBL_ADDR 0x42000
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#define IPQ807X_PPE_L1_C_SP_CFG_TBL (IPQ807X_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
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IPQ807X_PPE_L1_C_SP_CFG_TBL_ADDR)
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#define IPQ807X_PPE_L0_E_SP_CFG_TBL_ADDR 0x6000
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#define IPQ807X_PPE_L0_E_SP_CFG_TBL (IPQ807X_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
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IPQ807X_PPE_L0_E_SP_CFG_TBL_ADDR)
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#define IPQ807X_PPE_L1_E_SP_CFG_TBL_ADDR 0x44000
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#define IPQ807X_PPE_L1_E_SP_CFG_TBL (IPQ807X_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
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IPQ807X_PPE_L1_E_SP_CFG_TBL_ADDR)
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#define IPQ807X_PPE_FPGA_GPIO_BASE_ADDR 0x01008000
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#define IPQ807X_PPE_MAC_PORT_MUX_OFFSET 0x10
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#define IPQ807X_PPE_FPGA_GPIO_OFFSET 0xc000
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#define IPQ807X_PPE_FPGA_SCHED_OFFSET 0x47a000
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#define IPQ807X_PPE_TDM_CFG_DEPTH_OFFSET 0xb000
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#define IPQ807X_PPE_TDM_SCHED_DEPTH_OFFSET 0x400000
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#define IPQ807X_PPE_PORT_BRIDGE_CTRL_OFFSET 0x060300
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#define IPQ807X_PPE_TDM_CFG_DEPTH_VAL 0x80000064
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#define IPQ807X_PPE_MAC_PORT_MUX_OFFSET_VAL 0x15
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#define IPQ807X_PPE_TDM_SCHED_DEPTH_VAL 0x32
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#define IPQ807X_PPE_TDM_CFG_VALID 0x20
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#define IPQ807X_PPE_TDM_CFG_DIR_INGRESS 0x0
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#define IPQ807X_PPE_TDM_CFG_DIR_EGRESS 0x10
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#define IPQ807X_PPE_PORT_EDMA 0x0
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#define IPQ807X_PPE_PORT_QCOM1 0x1
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#define IPQ807X_PPE_PORT_QCOM2 0x2
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#define IPQ807X_PPE_PORT_QCOM3 0x3
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#define IPQ807X_PPE_PORT_QCOM4 0x4
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#define IPQ807X_PPE_PORT_XGMAC1 0x5
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#define IPQ807X_PPE_PORT_XGMAC2 0x6
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#define IPQ807X_PPE_PORT_CRYPTO1 0x7
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#define IPQ807X_PPE_PORT_BRIDGE_CTRL_PROMISC_EN 0x20000
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#define IPQ807X_PPE_PORT_BRIDGE_CTRL_TXMAC_EN 0x10000
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#define IPQ807X_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP 0x7f00
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#define IPQ807X_PPE_PORT_BRIDGE_CTRL_STATION_LRN_EN 0x8
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#define IPQ807X_PPE_PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN 0x1
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#define IPQ807X_PPE_PORT_EDMA_BITPOS 0x1
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#define IPQ807X_PPE_PORT_QCOM1_BITPOS (1 << IPQ807X_PPE_PORT_QCOM1)
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#define IPQ807X_PPE_PORT_QCOM2_BITPOS (1 << IPQ807X_PPE_PORT_QCOM2)
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#define IPQ807X_PPE_PORT_QCOM3_BITPOS (1 << IPQ807X_PPE_PORT_QCOM3)
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#define IPQ807X_PPE_PORT_QCOM4_BITPOS (1 << IPQ807X_PPE_PORT_QCOM4)
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#define IPQ807X_PPE_PORT_XGMAC1_BITPOS (1 << IPQ807X_PPE_PORT_XGMAC1)
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#define IPQ807X_PPE_PORT_XGMAC2_BITPOS (1 << IPQ807X_PPE_PORT_XGMAC2)
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#define IPQ807X_PPE_PORT_CRYPTO1_BITPOS (1 << IPQ807X_PPE_PORT_CRYPTO1)
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#define PPE_SWITCH_NSS_SWITCH_XGMAC0 0x3000
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#define NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION 0x4000
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#define USS (1 << 31)
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#define SS(i) (i << 29)
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#define JD (1 << 16)
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#define TE (1 << 0)
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#define NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION 0x4000
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#define MAC_RX_CONFIGURATION_ADDRESS 0x4
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#define RE (1 << 0)
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#define ACS (1 << 1)
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#define CST (1 << 2)
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#define MAC_PACKET_FILTER_INC 0x4000
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#define MAC_PACKET_FILTER_ADDRESS 0x8
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#define XGMAC_SPEED_SELECT_10000M 0
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#define XGMAC_SPEED_SELECT_5000M 1
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#define XGMAC_SPEED_SELECT_2500M 2
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#define XGMAC_SPEED_SELECT_1000M 3
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#define IPE_L2_BASE_ADDR 0x060000
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#define PORT_BRIDGE_CTRL_ADDRESS 0x300
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#define PORT_BRIDGE_CTRL_INC 0x4
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#define TX_MAC_EN (1 << 16)
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#define IPO_CSR_BASE_ADDR 0x0b0000
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#define IPO_RULE_REG_ADDRESS 0x0
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#define IPO_RULE_REG_INC 0x10
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#define IPO_MASK_REG_ADDRESS 0x2000
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#define IPO_MASK_REG_INC 0x10
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#define IPO_ACTION_ADDRESS 0x8000
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#define IPO_ACTION_INC 0x20
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