Mingkai Hu bbc8e053ba armv8/ls1043a: Implement workaround for erratum A009660 ... Memory controller performance is not optimal with default internal target queue register value, write required value for optimal DDR performance. Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>		2016-02-24 08:40:56 -08:00
..
arc	arc: cache - utilize IO coherency (AKA IOC) engine	2016-02-20 11:20:05 +03:00
arm	armv8/ls1043a: Implement workaround for erratum A009660	2016-02-24 08:40:56 -08:00
avr32
blackfin	Use correct spelling of "U-Boot"	2016-02-06 12:00:59 +01:00
m68k
microblaze	Use correct spelling of "U-Boot"	2016-02-06 12:00:59 +01:00
mips	Use correct spelling of "U-Boot"	2016-02-06 12:00:59 +01:00
nds32	Use correct spelling of "U-Boot"	2016-02-06 12:00:59 +01:00
nios2	nios2: set up the debug UART early	2016-02-06 15:14:25 +08:00
openrisc	openrisc: Fix build errors	2016-01-25 10:40:01 -05:00
powerpc	powerpc/SECURE_BOOT: Add PAMU driver	2016-02-24 08:40:55 -08:00
sandbox
sh
sparc	Use correct spelling of "U-Boot"	2016-02-06 12:00:59 +01:00
x86	x86: Add Intel Cougar Canyon 2 board	2016-02-21 13:42:52 +08:00
.gitignore
Kconfig