mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
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3a8f8f7b4b
Fidelix SPI NAND FM35X2GA has two planes namely plane 0 and plane 1. This change adds the support to calculate the plane bit accordingly and use the same for command formation. Change-Id: I6fb4b652e1c897f248cb9ad8914f67be7a7365f3 Signed-off-by: Kathiravan T <kathirav@codeaurora.org>
117 lines
3.8 KiB
C
117 lines
3.8 KiB
C
/*
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* Copyright (c) 2015 The Linux Foundation. All rights reserved.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef SPI_NAND_DEV_H
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#define SPI_NAND_DEV_H
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#define MTD_MAX_OOBFREE_ENTRIES_LARGE 32
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#ifdef MTD_MAX_ECCPOS_ENTRIES_LARGE
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#undef MTD_MAX_ECCPOS_ENTRIES_LARGE
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#define MTD_MAX_ECCPOS_ENTRIES_LARGE 640
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#endif
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#define INT_MAX ((int)(~0U>>1))
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/* Flash opcodes. */
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#define IPQ40XX_SPINAND_CMD_WREN 0x06 /* Write enable */
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#define IPQ40XX_SPINAND_CMD_WRDI 0x04 /* Write disable */
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#define IPQ40XX_SPINAND_CMD_GETFEA 0x0F /* Get feature */
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#define IPQ40XX_SPINAND_CMD_SETFEA 0x1F /* Set feature */
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#define IPQ40XX_SPINAND_CMD_READ 0x13 /* read data to cache */
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#define IPQ40XX_SPINAND_CMD_NORM_READ 0x03 /* Read data bytes (low frequency) */
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#define IPQ40XX_SPINAND_CMD_FAST_READ 0x0B /* Read data bytes (high frequency) */
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#define IPQ40XX_SPINAND_CMD_PLOAD 0x02 /* Program load */
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#define IPQ40XX_SPINAND_CMD_PROG 0x10 /* Program execute */
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#define IPQ40XX_SPINAND_CMD_ERASE 0xD8 /* Block erase */
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#define IPQ40XX_SPINAND_CMD_RDID 0x9F /* Read JEDEC ID */
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#define IPQ40XX_SPINAND_CMD_RESET 0xFF /* reset nand flash */
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#define IPQ40XX_SPINAND_CMD_DIESELECT 0xC2 /* Die Select */
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/* Flash Protection register */
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#define IPQ40XX_SPINAND_PROTEC_REG 0xA0
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#define IPQ40XX_SPINAND_PROTEC_BRWD 0x80
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#define IPQ40XX_SPINAND_PROTEC_BP2 0x20
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#define IPQ40XX_SPINAND_PROTEC_BP1 0x10
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#define IPQ40XX_SPINAND_PROTEC_BP0 0x08
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#define IPQ40XX_SPINAND_PROTEC_INV 0x04
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#define IPQ40XX_SPINAND_PROTEC_CMP 0x02
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#define IPQ40XX_SPINAND_PROTEC_BPx 0xC7
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/* Flash feature register */
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#define IPQ40XX_SPINAND_FEATURE_REG 0xB0
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#define IPQ40XX_SPINAND_FEATURE_OTPPRT 0x80
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#define IPQ40XX_SPINAND_FEATURE_OPTEN 0x40
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#define IPQ40XX_SPINAND_FEATURE_ECC_EN 0x10
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#define IPQ40XX_SPINAND_FEATURE_QE 0x01
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/* Flash status register. */
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#define IPQ40XX_SPINAND_STATUS_REG 0xC0
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#define IPQ40XX_SPINAND_STATUS_BUSY 0x1
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#define IPQ40XX_SPINAND_STATUS_WREN 0x2
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#define IPQ40XX_SPINAND_STATUS_EFAIL 0x4
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#define IPQ40XX_SPINAND_STATUS_PFAIL 0x8
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#define IPQ40XX_SPINAND_STATUS_ECCMASK 0x30
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#define IPQ40XX_SPINAND_STATUS_ECC(x) (x << 4)
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#define IPQ40XX_SPINAND_STATUS_ECC0 0x0
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#define IPQ40XX_SPINAND_STATUS_ECC1 0x1
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#define IPQ40XX_SPINAND_STATUS_ECC2 0x2
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#define IPQ40XX_SPINAND_STATUS_ECC3 0x3
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#define SPINAND_VERC_STATUS_ECCMASK 0x70
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#define SPINAND_VERC_STATUS_ERR 0x70
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#define STATUS_E_FAIL 0x04
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#define STATUS_P_FAIL 0x08
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struct spi_nand_flash_params {
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u8 id[4];
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u16 page_size;
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u16 pages_per_sector;
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u16 nr_sectors;
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u32 oob_size;
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u32 erase_size;
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u8 no_of_dies;
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int prev_die_id;
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u8 plane_id;
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u8 protec_bpx;
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u64 pages_per_die;
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void (*norm_read_cmd) (u8 *cmd, int column);
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int (*verify_ecc) (int status);
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int (*die_select) (struct mtd_info *mtd,
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struct spi_flash *flash, int die_id);
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const char *name;
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};
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struct ipq40xx_spinand_info {
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struct nand_hw_control controller;
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struct mtd_info *mtd;
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struct nand_chip *chip;
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struct spi_flash *flash;
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const struct spi_nand_flash_params *params;
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uint8_t *cmd;
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uint8_t chip_ver;
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uint16_t cmd_len;
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uint16_t ob_required;
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uint32_t status;
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};
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#define ECC_ERR 1
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#define ECC_CORRECTED 2
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#define SPINAND_3BIT_ECC_MASK 0x70
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#define SPINAND_3BIT_ECC_ERROR 0x70
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#define SPINAND_3BIT_ECC_BF_THRESHOLD 0x40
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#define SPINAND_2BIT_ECC_MASK 0x30
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#define SPINAND_2BIT_ECC_ERROR 0x20
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#define SPINAND_2BIT_ECC_CORRECTED 0x10
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#define SPINAND_2BIT_ECC_CORRECTED_TOSHIBA 0x30
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#endif
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