mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2026-03-14 21:10:27 +01:00
c4c0122082
This change initializes the CPU PLL , configures the timer, DRAM & enables the serial console for the AP152 target. Change-Id: If2a6884813250c09a856c3cb2e1783bf3940619c Signed-off-by: Prabhu Jayakumar <pjayak@codeaurora.org>
243 lines
6.1 KiB
C
243 lines
6.1 KiB
C
/*
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* Copyright (c) 2016 The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <asm/addrspace.h>
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#include <asm/types.h>
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#include <config.h>
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#include <atheros.h>
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#include <serial.h>
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int qca_serial_init(void)
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{
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//#if !defined(CONFIG_ATH_EMULATION)
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uint32_t div, val;
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div = ath_uart_freq() / (16 * CONFIG_BAUDRATE);
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#if defined(CONFIG_SCO_SLAVE_CONNECTED)
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val = ath_reg_rd(GPIO_OE_ADDRESS) & (~0xcbf410u);
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#elif defined(CONFIG_MACH_QCA956x)
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val = ath_reg_rd(GPIO_OE_ADDRESS) & 0xbbfdf6;
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#else
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val = ath_reg_rd(GPIO_OE_ADDRESS) & (~0xcffc10u);
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#endif
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#if defined(CONFIG_ATH_SPI_NAND_CS_GPIO)
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val |= 1 << CONFIG_ATH_SPI_NAND_CS_GPIO;
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#endif
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#if defined(CONFIG_ATH_SPI_CS1_GPIO)
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val |= 1 << CONFIG_ATH_SPI_CS1_GPIO;
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#endif
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ath_reg_wr(GPIO_OE_ADDRESS, val);
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#ifdef CONFIG_MACH_QCA956x
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#if defined(UART_RX20_TX22)
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val = (ath_reg_rd(GPIO_OE_ADDRESS) & (~0x400000));
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ath_reg_wr(GPIO_OE_ADDRESS, val);
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ath_reg_rmw_clear(GPIO_OUT_FUNCTION5_ADDRESS,
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GPIO_OUT_FUNCTION5_ENABLE_GPIO_22_MASK);
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ath_reg_rmw_set(GPIO_OUT_FUNCTION5_ADDRESS,
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GPIO_OUT_FUNCTION5_ENABLE_GPIO_22_SET(0x16));
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ath_reg_rmw_clear(GPIO_IN_ENABLE0_ADDRESS,
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GPIO_IN_ENABLE0_UART_SIN_MASK);
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ath_reg_rmw_set(GPIO_IN_ENABLE0_ADDRESS,
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GPIO_IN_ENABLE0_UART_SIN_SET(0x14));
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#elif defined(UART_RX18_TX22)
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val = (ath_reg_rd(GPIO_OE_ADDRESS) & (~0x400000)) | 0x40000;
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ath_reg_wr(GPIO_OE_ADDRESS, val);
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ath_reg_rmw_clear(GPIO_OUT_FUNCTION5_ADDRESS,
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GPIO_OUT_FUNCTION5_ENABLE_GPIO_22_MASK);
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ath_reg_rmw_set(GPIO_OUT_FUNCTION5_ADDRESS,
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GPIO_OUT_FUNCTION5_ENABLE_GPIO_22_SET(0x16));
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ath_reg_rmw_clear(GPIO_IN_ENABLE0_ADDRESS,
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GPIO_IN_ENABLE0_UART_SIN_MASK);
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ath_reg_rmw_set(GPIO_IN_ENABLE0_ADDRESS,
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GPIO_IN_ENABLE0_UART_SIN_SET(0x12));
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#elif defined(UART_RX18_TX20)
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val = (ath_reg_rd(GPIO_OE_ADDRESS) & (~0x100000)) | 0x40000;
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ath_reg_wr(GPIO_OE_ADDRESS, val);
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val = ath_reg_rd(GPIO_OUT_ADDRESS) | 0xeffff6;
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ath_reg_wr(GPIO_OUT_ADDRESS, val);
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ath_reg_rmw_clear(GPIO_OUT_FUNCTION5_ADDRESS,
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GPIO_OUT_FUNCTION5_ENABLE_GPIO_20_MASK);
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ath_reg_rmw_set(GPIO_OUT_FUNCTION5_ADDRESS,
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GPIO_OUT_FUNCTION5_ENABLE_GPIO_20_SET(0x16));
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ath_reg_rmw_clear(GPIO_IN_ENABLE0_ADDRESS,
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GPIO_IN_ENABLE0_UART_SIN_MASK);
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ath_reg_rmw_set(GPIO_IN_ENABLE0_ADDRESS,
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GPIO_IN_ENABLE0_UART_SIN_SET(0x12));
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#elif defined(UART_RX24_TX20)
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// Turn off LED before XLNA swap to GPO
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val = ath_reg_rd(GPIO_OUT_ADDRESS) | 0xaffff6;
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ath_reg_wr(GPIO_OUT_ADDRESS, val);
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//Switch GPI and GPO and XPA, XLNA
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ath_reg_wr(GPIO_FUNCTION_ADDRESS, 0x8000);
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val = (ath_reg_rd(GPIO_OE_ADDRESS) & (~0x100000)) | 0x1000000;
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ath_reg_wr(GPIO_OE_ADDRESS, val);
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ath_reg_rmw_set(GPIO_OUT_FUNCTION5_ADDRESS,
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GPIO_OUT_FUNCTION5_ENABLE_GPIO_20_SET(0x16));
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ath_reg_rmw_clear(GPIO_IN_ENABLE0_ADDRESS,
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GPIO_IN_ENABLE0_UART_SIN_SET(0xff));
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ath_reg_rmw_set(GPIO_IN_ENABLE0_ADDRESS,
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GPIO_IN_ENABLE0_UART_SIN_SET(0x18));
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#elif defined(TEST_BOARD_UART)
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//Switch GPI and GPO and XPA1, ANTC
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ath_reg_wr(GPIO_FUNCTION_ADDRESS, 0xc000);
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val = ath_reg_rd(GPIO_OE_ADDRESS) & (~0x2000);
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ath_reg_wr(GPIO_OE_ADDRESS, val);
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ath_reg_rmw_clear(GPIO_OUT_FUNCTION3_ADDRESS,
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GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_MASK);
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ath_reg_rmw_set(GPIO_OUT_FUNCTION3_ADDRESS,
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GPIO_OUT_FUNCTION3_ENABLE_GPIO_13_SET(0x16));
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ath_reg_rmw_clear(GPIO_IN_ENABLE0_ADDRESS,
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GPIO_IN_ENABLE0_UART_SIN_SET(0xff));
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ath_reg_rmw_set(GPIO_IN_ENABLE0_ADDRESS,
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GPIO_IN_ENABLE0_UART_SIN_SET(0x17));
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#else
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val = (ath_reg_rd(GPIO_OE_ADDRESS) & (~0x100000)) | 0x80000;
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ath_reg_wr(GPIO_OE_ADDRESS, val);
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ath_reg_rmw_set(GPIO_OUT_FUNCTION5_ADDRESS,
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GPIO_OUT_FUNCTION5_ENABLE_GPIO_20_SET(0x16));
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ath_reg_rmw_clear(GPIO_IN_ENABLE0_ADDRESS,
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GPIO_IN_ENABLE0_UART_SIN_SET(0xff));
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ath_reg_rmw_set(GPIO_IN_ENABLE0_ADDRESS,
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GPIO_IN_ENABLE0_UART_SIN_SET(0x13));
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#endif
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val = ath_reg_rd(GPIO_OUT_ADDRESS) | 0xaffff6;
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ath_reg_wr(GPIO_OUT_ADDRESS, val);
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val = ath_reg_rd(GPIO_SPARE_ADDRESS);
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ath_reg_wr(GPIO_SPARE_ADDRESS, (val | 0x8402));
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#else
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ath_reg_rmw_set(GPIO_OUT_FUNCTION2_ADDRESS,
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GPIO_OUT_FUNCTION2_ENABLE_GPIO_10_SET(0x16));
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ath_reg_rmw_clear(GPIO_IN_ENABLE0_ADDRESS,
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GPIO_IN_ENABLE0_UART_SIN_SET(0xff));
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ath_reg_rmw_set(GPIO_IN_ENABLE0_ADDRESS,
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GPIO_IN_ENABLE0_UART_SIN_SET(0x9));
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val = ath_reg_rd(GPIO_OUT_ADDRESS) | 0xcffc10u;
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ath_reg_wr(GPIO_OUT_ADDRESS, val);
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val = ath_reg_rd(GPIO_SPARE_ADDRESS);
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ath_reg_wr(GPIO_SPARE_ADDRESS, (val | 0x8402));
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ath_reg_wr(GPIO_OUT_ADDRESS, 0x2f);
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#endif
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/*
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* set DIAB bit
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*/
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ath_uart_wr(OFS_LINE_CONTROL, 0x80);
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/* set divisor */
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ath_uart_wr(OFS_DIVISOR_LSB, (div & 0xff));
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ath_uart_wr(OFS_DIVISOR_MSB, ((div >> 8) & 0xff));
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/* clear DIAB bit*/
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ath_uart_wr(OFS_LINE_CONTROL, 0x00);
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/* set data format */
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ath_uart_wr(OFS_DATA_FORMAT, 0x3);
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ath_uart_wr(OFS_INTR_ENABLE, 0);
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//#endif
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return 0;
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}
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int qca_serial_tstc (void)
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{
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return(ath_uart_rd(OFS_LINE_STATUS) & 0x1);
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}
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u8 qca_serial_getc(void)
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{
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while(!serial_tstc());
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return ath_uart_rd(OFS_RCV_BUFFER);
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}
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void qca_serial_putc(u8 byte)
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{
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if (byte == '\n') serial_putc ('\r');
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while (((ath_uart_rd(OFS_LINE_STATUS)) & 0x20) == 0x0);
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ath_uart_wr(OFS_SEND_BUFFER, byte);
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}
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void qca_serial_setbrg (void)
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{
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}
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void qca_serial_puts (const char *s)
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{
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while (*s)
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{
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serial_putc (*s++);
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}
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}
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static struct serial_device qca956x_serial_drv = {
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.name = "qca956x_serial",
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.start = qca_serial_init,
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.stop = NULL,
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.setbrg = NULL,
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.putc = qca_serial_putc,
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.puts = qca_serial_puts,
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.getc = qca_serial_getc,
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.tstc = qca_serial_tstc,
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};
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void qca_serial_initialize(void)
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{
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serial_register(&qca956x_serial_drv);
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}
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__weak struct serial_device *default_serial_console(void)
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{
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return &qca956x_serial_drv;
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}
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