mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2026-03-14 21:10:27 +01:00
88f81ffced
This change adds support to enable multiple I2C bus on all IPQ platforms. Removed the device specific changes and updated in a generic way to support multiple I2C on all the IPQ platforms. Change-Id: Ie13dd744c6317fc9245bc88781e79a9fb3621a62 Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
82 lines
2.3 KiB
C
82 lines
2.3 KiB
C
/*
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* Copyright (c) 2015-2016, 2018 The Linux Foundation. All rights reserved.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch-ipq6018/clk.h>
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#include <asm/errno.h>
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static void uart_configure_mux(u8 id)
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{
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unsigned long cfg_rcgr;
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cfg_rcgr = readl(GCC_BLSP1_UART_APPS_CFG_RCGR(id));
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/* Clear mode, src sel, src div */
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cfg_rcgr &= ~(GCC_UART_CFG_RCGR_MODE_MASK |
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GCC_UART_CFG_RCGR_SRCSEL_MASK |
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GCC_UART_CFG_RCGR_SRCDIV_MASK);
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cfg_rcgr |= ((UART_RCGR_SRC_SEL << GCC_UART_CFG_RCGR_SRCSEL_SHIFT)
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& GCC_UART_CFG_RCGR_SRCSEL_MASK);
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cfg_rcgr |= ((UART_RCGR_SRC_DIV << GCC_UART_CFG_RCGR_SRCDIV_SHIFT)
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& GCC_UART_CFG_RCGR_SRCDIV_MASK);
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cfg_rcgr |= ((UART_RCGR_MODE << GCC_UART_CFG_RCGR_MODE_SHIFT)
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& GCC_UART_CFG_RCGR_MODE_MASK);
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writel(cfg_rcgr, GCC_BLSP1_UART_APPS_CFG_RCGR(id));
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}
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static int uart_trigger_update(u8 id)
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{
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unsigned long cmd_rcgr;
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int timeout = 0;
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cmd_rcgr = readl(GCC_BLSP1_UART_APPS_CMD_RCGR(id));
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cmd_rcgr |= UART_CMD_RCGR_UPDATE;
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writel(cmd_rcgr, GCC_BLSP1_UART_APPS_CMD_RCGR(id));
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while (readl(GCC_BLSP1_UART_APPS_CMD_RCGR(id)) & UART_CMD_RCGR_UPDATE) {
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if (timeout++ >= CLOCK_UPDATE_TIMEOUT_US) {
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printf("Timeout waiting for UART clock update\n");
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return -ETIMEDOUT;
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}
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udelay(1);
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}
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cmd_rcgr = readl(GCC_BLSP1_UART_APPS_CMD_RCGR(id));
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return 0;
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}
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int uart_clock_config(struct ipq_serial_platdata *plat)
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{
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unsigned long cbcr_val;
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int ret;
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uart_configure_mux(plat->port_id);
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writel(plat->m_value, GCC_BLSP1_UART_APPS_M(plat->port_id));
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writel(NOT_N_MINUS_M(plat->n_value, plat->m_value),
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GCC_BLSP1_UART_APPS_N(plat->port_id));
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writel(NOT_2D(plat->d_value), GCC_BLSP1_UART_APPS_D(plat->port_id));
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ret = uart_trigger_update(plat->port_id);
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if (ret)
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return ret;
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cbcr_val = readl(GCC_BLSP1_UART_APPS_CBCR(plat->port_id));
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cbcr_val |= UART_CBCR_CLK_ENABLE;
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writel(cbcr_val, GCC_BLSP1_UART_APPS_CBCR(plat->port_id));
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return 0;
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}
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