mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2026-03-14 21:10:27 +01:00
a662e31aee
This change will add the clock setting for qpic-serial nand Change-Id: Iae53933423572e35126ceeb359b82d1078d09bf2 Signed-off-by: Timple Raj M <quic_timple@quicinc.com>
116 lines
3.5 KiB
C
116 lines
3.5 KiB
C
/*
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* Copyright (c) 2015-2016, 2018-2020 The Linux Foundation. All rights reserved.
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*
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* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch-qca-common/clk.h>
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#include <asm/errno.h>
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#include <fdtdec.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_IPQ_I2C
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void i2c_clock_config(void)
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{
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int cfg, i2c_id;
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int i2c_node;
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const u32 *i2c_base;
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int i;
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char alias[6];
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for (i = 0; i < CONFIG_IPQ_MAX_BLSP_QUPS; i++) {
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memset(alias, 0, 6);
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snprintf(alias, 5, "i2c%d", i);
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i2c_node = fdt_path_offset(gd->fdt_blob, alias);
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if (i2c_node >= 0) {
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i2c_base = fdt_getprop(gd->fdt_blob, i2c_node, "reg", NULL);
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if (i2c_base) {
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i2c_id = I2C_PORT_ID(fdt32_to_cpu(i2c_base[0]));
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/* Configure qup1_i2c_apps_clk_src */
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cfg = (GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_SEL |
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GCC_BLSP1_QUP1_I2C_APPS_CFG_RCGR_SRC_DIV);
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writel(cfg, GCC_BLSP1_QUP_I2C_APPS_CFG_RCGR(i2c_id));
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writel(CMD_UPDATE, GCC_BLSP1_QUP_I2C_APPS_CMD_RCGR(i2c_id));
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mdelay(100);
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writel(ROOT_EN, GCC_BLSP1_QUP_I2C_APPS_CMD_RCGR(i2c_id));
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/* Configure CBCR */
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writel(CLK_ENABLE, GCC_BLSP1_QUP_I2C_APPS_CBCR(i2c_id));
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}
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}
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}
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}
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#endif
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#if defined(CONFIG_QPIC_NAND) && defined(CONFIG_QSPI_SERIAL_TRAINING)
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__weak void qpic_set_clk_rate(unsigned int clk_rate, int blk_type,
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int req_clk_src_type)
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{
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switch (blk_type) {
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case QPIC_IO_MACRO_CLK:
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/* select the clk source for IO_PAD_MACRO
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* clk source wil be either XO = 24MHz. or GPLL0 = 800MHz.
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*/
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if (req_clk_src_type == XO_CLK_SRC) {
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/* default XO clock will enabled
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* i.e XO clock = 24MHz.
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* so div value will 0.
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* Input clock to IO_MACRO will be divided by 4 by default
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* by hardware and then taht clock will be go on bus.
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* i.e 24/4MHz = 6MHz i.e 6MHz will go onto the bus.
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*/
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writel(0x0, GCC_QPIC_IO_MACRO_CFG_RCGR);
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} else if (req_clk_src_type == GPLL0_CLK_SRC) {
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/* selct GPLL0 clock source 800MHz
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* so 800/4 = 200MHz.
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* Input clock to IO_MACRO will be divided by 4 by default
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* by hardware and then that clock will be go on bus.
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* i.e 200/4MHz = 50MHz i.e 50MHz will go onto the bus.
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*/
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if (clk_rate == IO_MACRO_CLK_320_MHZ)
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writel(0x104, GCC_QPIC_IO_MACRO_CFG_RCGR);
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else if (clk_rate == IO_MACRO_CLK_266_MHZ)
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writel(0x105, GCC_QPIC_IO_MACRO_CFG_RCGR);
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else if (clk_rate == IO_MACRO_CLK_228_MHZ)
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writel(0x106, GCC_QPIC_IO_MACRO_CFG_RCGR);
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else if (clk_rate == IO_MACRO_CLK_100_MHZ)
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writel(0x10F, GCC_QPIC_IO_MACRO_CFG_RCGR);
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else if (clk_rate == IO_MACRO_CLK_200_MHZ)
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writel(0x107, GCC_QPIC_IO_MACRO_CFG_RCGR);
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} else {
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printf("wrong clk src selection requested.\n");
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}
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/* Enablle update bit to update the new configuration */
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writel((UPDATE_EN | readl(GCC_QPIC_IO_MACRO_CMD_RCGR)),
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GCC_QPIC_IO_MACRO_CMD_RCGR);
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/* Enable the QPIC_IO_MACRO_CLK */
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writel(0x1, GCC_QPIC_IO_MACRO_CBCR);
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break;
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case QPIC_CORE_CLK:
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/* To DO if needed for QPIC core clock setting */
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break;
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default:
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printf("wrong qpic block type\n");
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break;
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}
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}
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#endif
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