Ruchika Gupta 668ec87f52 powerpc: e6500: Lock/unlock 1 cache instead of L1 as init_ram ... For E6500 cores, L2 cache has been used as init_ram. L1 cache is a write through cache on E6500.If lines are not locked in both L1 and L2 caches, crashes are observed during secure boot. This patch locks/ unlocks both L1 and L2 cache to prevent the crash. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>		2017-04-17 09:03:30 -07:00
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cpu	powerpc: e6500: Lock/unlock 1 cache instead of L1 as init_ram	2017-04-17 09:03:30 -07:00
dts	ppc: dts: Add device tree for xilix-ppc4xx-generic	2016-01-27 15:43:01 +01:00
include/asm	powerpc: T1042RDB: SECURE BOOT: Remove CONFIG_CMD_BLOB from SPL compilation	2017-04-17 09:03:30 -07:00
lib	powerpc: Move setup_board_extra() into a PPC file	2017-04-05 16:36:55 -04:00
config.mk	arm, powerpc: Update cc-version tests to check for cc-name as well	2016-01-25 10:39:44 -05:00
Kconfig	fsl_ddr: Move DDR config options to driver Kconfig	2017-01-04 19:40:41 -05:00
Makefile	Kbuild: introduce Makefile in arch/$ARCH/	2014-12-08 09:35:45 -05:00