mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
a95cba141c
Change-Id: I4d646c1a89d90febd573ae92980e0c665b1dc060 Signed-off-by: Ram Kumar D <quic_ramd@quicinc.com>
266 lines
8.7 KiB
C
266 lines
8.7 KiB
C
/*
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**************************************************************************
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* Copyright (c) 2016-2019, 2021, The Linux Foundation. All rights reserved.
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*
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* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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**************************************************************************
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*/
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#include <common.h>
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#include <net.h>
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#include <asm-generic/errno.h>
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#include <asm/io.h>
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#include <malloc.h>
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#include <phy.h>
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#include <net.h>
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#include <miiphy.h>
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#define DEVSOC_PPE_BASE_ADDR 0x3a000000
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#define PORT1 1
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#define PORT2 2
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#define DEVSOC_PORT5_MUX_PCS_UNIPHY0 0x0
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#define DEVSOC_PORT5_MUX_PCS_UNIPHY1 0x1
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#define PORT_GMAC_TYPE 1
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#define PORT_XGMAC_TYPE 2
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#define DEVSOC_PORT_MUX_MAC_TYPE 0
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#define DEVSOC_PORT_MUX_XMAC_TYPE 1
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struct port_mux_ctrl {
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uint32_t port1_pcs_sel:1;
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uint32_t port2_pcs_sel:1;
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uint32_t _reserved0:6;
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uint32_t port1_mac_sel:1;
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uint32_t port2_mac_sel:1;
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uint32_t _reserved1:22;
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};
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union port_mux_ctrl_u {
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uint32_t val;
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struct port_mux_ctrl bf;
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};
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enum {
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TCP_PKT,
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UDP_PKT,
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};
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#define ADPT_ACL_HPPE_IPV4_DIP_RULE 4
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#define ADPT_ACL_HPPE_MAC_SA_RULE 1
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#define ADPT_ACL_HPPE_MAC_DA_RULE 0
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#define MAX_RULE 512
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struct ipo_rule_reg {
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uint32_t rule_field_0:32;
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uint32_t rule_field_1:20;
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uint32_t fake_mac_header:1;
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uint32_t range_en:1;
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uint32_t inverse_en:1;
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uint32_t rule_type:5;
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uint32_t src_type:3;
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uint32_t src_0:1;
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uint32_t src_1:7;
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uint32_t pri:9;
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uint32_t res_chain:1;
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uint32_t post_routing_en:1;
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uint32_t _reserved0:14;
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};
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union ipo_rule_reg_u {
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uint32_t val[3];
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struct ipo_rule_reg bf;
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};
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struct ipo_mask_reg {
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uint32_t maskfield_0:32;
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uint32_t maskfield_1:21;
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uint32_t _reserved0:11;
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};
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union ipo_mask_reg_u {
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uint32_t val[2];
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struct ipo_mask_reg bf;
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};
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struct ipo_action {
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uint32_t dest_info_change_en:1;
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uint32_t fwd_cmd:2;
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uint32_t _reserved0:15;
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uint32_t bypass_bitmap_0:14;
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uint32_t bypass_bitmap_1:18;
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uint32_t _reserved1:14;
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uint32_t _reserved2:32;
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uint32_t _reserved3:32;
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uint32_t _reserved4:32;
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};
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union ipo_action_u {
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uint32_t val[5];
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struct ipo_action bf;
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};
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#define DEVSOC_PORT_MUX_CTRL 0x10
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#define DEVSOC_PORT_MUX_CTRL_NUM 1
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#define DEVSOC_PORT_MUX_CTRL_INC 0x4
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#define DEVSOC_PORT_MUX_CTRL_DEFAULT 0x0
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#define PORT_PHY_STATUS_ADDRESS 0x44
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#define PORT_PHY_STATUS_PORT5_1_OFFSET 8
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#define PORT_PHY_STATUS_PORT6_OFFSET 16
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#define DEVSOC_PPE_IPE_L3_BASE_ADDR 0x200000
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#define DEVSOC_PPE_L3_VP_PORT_TBL_ADDR (DEVSOC_PPE_IPE_L3_BASE_ADDR + 0x4000)
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#define DEVSOC_PPE_L3_VP_PORT_TBL_INC 0x10
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#define DEVSOC_PPE_TL_PORT_VP_TBL_ADDR 0x302000
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#define DEVSOC_PPE_MRU_MTU_CTRL_TBL_ADDR 0x65000
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#define DEVSOC_PPE_MC_MTU_CTRL_TBL_ADDR 0x60a00
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#define DEVSOC_PPE_PORT_EG_VLAN_TBL_ADDR 0x20020
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#define DEVSOC_PPE_UCAST_QUEUE_AC_EN_BASE_ADDR 0x848000
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#define DEVSOC_PPE_MCAST_QUEUE_AC_EN_BASE_ADDR 0x84a000
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#define DEVSOC_PPE_QUEUE_MANAGER_BASE_ADDR 0x800000
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#define DEVSOC_PPE_UCAST_QUEUE_MAP_TBL_ADDR 0x10000
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#define DEVSOC_PPE_UCAST_QUEUE_MAP_TBL_INC 0x10
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#define DEVSOC_PPE_QM_UQM_TBL (DEVSOC_PPE_QUEUE_MANAGER_BASE_ADDR +\
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DEVSOC_PPE_UCAST_QUEUE_MAP_TBL_ADDR)
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#define DEVSOC_PPE_UCAST_PRIORITY_MAP_TBL_ADDR 0x42000
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#define DEVSOC_PPE_QM_UPM_TBL (DEVSOC_PPE_QUEUE_MANAGER_BASE_ADDR +\
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DEVSOC_PPE_UCAST_PRIORITY_MAP_TBL_ADDR)
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#define DEVSOC_PPE_STP_BASE 0x060100
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#define DEVSOC_PPE_MAC_ENABLE 0x001000
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#define DEVSOC_PPE_MAC_SPEED 0x001004
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#define DEVSOC_PPE_MAC_MIB_CTL 0x001034
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#define DEVSOC_PPE_TRAFFIC_MANAGER_BASE_ADDR 0x400000
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#define DEVSOC_PPE_TM_SHP_CFG_L0_OFFSET 0x00000030
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#define DEVSOC_PPE_TM_SHP_CFG_L1_OFFSET 0x00000034
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#define DEVSOC_PPE_TM_SHP_CFG_L0 DEVSOC_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
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DEVSOC_PPE_TM_SHP_CFG_L0_OFFSET
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#define DEVSOC_PPE_TM_SHP_CFG_L1 DEVSOC_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
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DEVSOC_PPE_TM_SHP_CFG_L1_OFFSET
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#define DEVSOC_PPE_L0_FLOW_PORT_MAP_TBL_ADDR 0x10000
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#define DEVSOC_PPE_L0_FLOW_PORT_MAP_TBL_INC 0x10
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#define DEVSOC_PPE_L0_FLOW_PORT_MAP_TBL (DEVSOC_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
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DEVSOC_PPE_L0_FLOW_PORT_MAP_TBL_ADDR)
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#define DEVSOC_PPE_L0_FLOW_MAP_TBL_ADDR 0x2000
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#define DEVSOC_PPE_L0_FLOW_MAP_TBL_INC 0x10
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#define DEVSOC_PPE_L0_FLOW_MAP_TBL (DEVSOC_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
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DEVSOC_PPE_L0_FLOW_MAP_TBL_ADDR)
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#define DEVSOC_PPE_L1_FLOW_PORT_MAP_TBL_ADDR 0x46000
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#define DEVSOC_PPE_L1_FLOW_PORT_MAP_TBL_INC 0x10
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#define DEVSOC_PPE_L1_FLOW_PORT_MAP_TBL (DEVSOC_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
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DEVSOC_PPE_L1_FLOW_PORT_MAP_TBL_ADDR)
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#define DEVSOC_PPE_L1_FLOW_MAP_TBL_ADDR 0x40000
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#define DEVSOC_PPE_L1_FLOW_MAP_TBL_INC 0x10
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#define DEVSOC_PPE_L1_FLOW_MAP_TBL (DEVSOC_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
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DEVSOC_PPE_L1_FLOW_MAP_TBL_ADDR)
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#define DEVSOC_PPE_L0_C_SP_CFG_TBL_ADDR 0x4000
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#define DEVSOC_PPE_L0_C_SP_CFG_TBL (DEVSOC_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
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DEVSOC_PPE_L0_C_SP_CFG_TBL_ADDR)
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#define DEVSOC_PPE_L1_C_SP_CFG_TBL_ADDR 0x42000
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#define DEVSOC_PPE_L1_C_SP_CFG_TBL (DEVSOC_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
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DEVSOC_PPE_L1_C_SP_CFG_TBL_ADDR)
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#define DEVSOC_PPE_L0_E_SP_CFG_TBL_ADDR 0x6000
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#define DEVSOC_PPE_L0_E_SP_CFG_TBL (DEVSOC_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
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DEVSOC_PPE_L0_E_SP_CFG_TBL_ADDR)
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#define DEVSOC_PPE_L1_E_SP_CFG_TBL_ADDR 0x44000
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#define DEVSOC_PPE_L1_E_SP_CFG_TBL (DEVSOC_PPE_TRAFFIC_MANAGER_BASE_ADDR +\
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DEVSOC_PPE_L1_E_SP_CFG_TBL_ADDR)
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#define DEVSOC_PPE_FPGA_GPIO_BASE_ADDR 0x01008000
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#define DEVSOC_PPE_MAC_PORT_MUX_OFFSET 0x10
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#define DEVSOC_PPE_FPGA_GPIO_OFFSET 0xc000
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#define DEVSOC_PPE_FPGA_SCHED_OFFSET 0x47a000
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#define DEVSOC_PPE_TDM_CFG_DEPTH_OFFSET 0xb000
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#define DEVSOC_PPE_TDM_SCHED_DEPTH_OFFSET 0x400000
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#define DEVSOC_PPE_PORT_BRIDGE_CTRL_OFFSET 0x060300
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#define DEVSOC_PPE_TDM_CFG_DEPTH_VAL 0x80000064
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#define DEVSOC_PPE_MAC_PORT_MUX_OFFSET_VAL 0x15
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#define DEVSOC_PPE_TDM_SCHED_DEPTH_VAL 0x32
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#define DEVSOC_PPE_TDM_CFG_VALID 0x20
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#define DEVSOC_PPE_TDM_CFG_DIR_INGRESS 0x0
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#define DEVSOC_PPE_TDM_CFG_DIR_EGRESS 0x10
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#define DEVSOC_PPE_PORT_EDMA 0x0
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#define DEVSOC_PPE_PORT_QTI1 0x1
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#define DEVSOC_PPE_PORT_QTI2 0x2
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#define DEVSOC_PPE_PORT_QTI3 0x3
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#define DEVSOC_PPE_PORT_QTI4 0x4
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#define DEVSOC_PPE_PORT_XGMAC1 0x5
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#define DEVSOC_PPE_PORT_XGMAC2 0x6
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#define DEVSOC_PPE_PORT_CRYPTO1 0x7
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#define DEVSOC_PPE_PORT_BRIDGE_CTRL_PROMISC_EN 0x20000
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#define DEVSOC_PPE_PORT_BRIDGE_CTRL_TXMAC_EN 0x10000
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#define DEVSOC_PPE_PORT_BRIDGE_CTRL_PORT_ISOLATION_BMP 0x7f00
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#define DEVSOC_PPE_PORT_BRIDGE_CTRL_STATION_LRN_EN 0x8
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#define DEVSOC_PPE_PORT_BRIDGE_CTRL_NEW_ADDR_LRN_EN 0x1
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#define DEVSOC_PPE_PORT_EDMA_BITPOS 0x1
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#define DEVSOC_PPE_PORT_QTI1_BITPOS (1 << DEVSOC_PPE_PORT_QTI1)
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#define DEVSOC_PPE_PORT_QTI2_BITPOS (1 << DEVSOC_PPE_PORT_QTI2)
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#define DEVSOC_PPE_PORT_QTI3_BITPOS (1 << DEVSOC_PPE_PORT_QTI3)
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#define DEVSOC_PPE_PORT_QTI4_BITPOS (1 << DEVSOC_PPE_PORT_QTI4)
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#define DEVSOC_PPE_PORT_XGMAC1_BITPOS (1 << DEVSOC_PPE_PORT_XGMAC1)
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#define DEVSOC_PPE_PORT_XGMAC2_BITPOS (1 << DEVSOC_PPE_PORT_XGMAC2)
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#define DEVSOC_PPE_PORT_CRYPTO1_BITPOS (1 << DEVSOC_PPE_PORT_CRYPTO1)
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#define PPE_SWITCH_NSS_SWITCH_XGMAC0 0x500000
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#define NSS_SWITCH_XGMAC_MAC_TX_CONFIGURATION 0x4000
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#define USS (1 << 31)
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#define SS(i) (i << 29)
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#define JD (1 << 16)
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#define TE (1 << 0)
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#define NSS_SWITCH_XGMAC_MAC_RX_CONFIGURATION 0x4000
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#define MAC_RX_CONFIGURATION_ADDRESS 0x4
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#define RE (1 << 0)
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#define ACS (1 << 1)
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#define CST (1 << 2)
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#define MAC_PACKET_FILTER_INC 0x4000
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#define MAC_PACKET_FILTER_ADDRESS 0x8
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#define XGMAC_SPEED_SELECT_10000M 0
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#define XGMAC_SPEED_SELECT_5000M 1
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#define XGMAC_SPEED_SELECT_2500M 2
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#define XGMAC_SPEED_SELECT_1000M 3
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#define IPE_L2_BASE_ADDR 0x060000
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#define PORT_BRIDGE_CTRL_ADDRESS 0x300
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#define PORT_BRIDGE_CTRL_INC 0x4
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#define TX_MAC_EN (1 << 16)
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#define IPO_CSR_BASE_ADDR 0x0b0000
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#define IPO_RULE_REG_ADDRESS 0x0
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#define IPO_RULE_REG_INC 0x10
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#define IPO_MASK_REG_ADDRESS 0x2000
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#define IPO_MASK_REG_INC 0x10
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#define IPO_ACTION_ADDRESS 0x8000
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#define IPO_ACTION_INC 0x20
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