Aneesh Bansal 82eda68444 powerpc/mpc85xx: set L2PE in L2CSR0 before enabling L2 cache ... While enabling L2 cache, the value of L2PE (L2 cache parity/ECC error checking enable) must not be changed while the L2 cache is enabled. So, L2PE must be set before enabling L2 cache. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>		2016-05-24 10:31:21 -07:00
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cpu	powerpc/mpc85xx: set L2PE in L2CSR0 before enabling L2 cache	2016-05-24 10:31:21 -07:00
dts	ppc: dts: Add device tree for xilix-ppc4xx-generic	2016-01-27 15:43:01 +01:00
include/asm	Kconfig: Move CONFIG_FIT and related options to Kconfig	2016-03-14 19:18:07 -04:00
lib	powerpc: Disable flush or invalidate dcache by range for some SoCs	2016-05-19 10:47:11 -07:00
config.mk	arm, powerpc: Update cc-version tests to check for cc-name as well	2016-01-25 10:39:44 -05:00
Kconfig	kbuild: create symbolic link only for ARM, AVR32, SPARC, PowerPC, x86	2015-07-27 15:02:00 -04:00
Makefile	Kbuild: introduce Makefile in arch/$ARCH/	2014-12-08 09:35:45 -05:00