Paul Burton 639200f6a0 MIPS: Ensure cache ops complete in mips_cache_reset ... Ensure that cache operations complete before returning from mips_cache_reset by placing a completion barrier (sync instruction) before the return. Without this there is no guarantee that the cache ops will complete before any subsequent memory accesses, since they are indexed cache ops & thus not implicitly ordered with memory accesses. Signed-off-by: Paul Burton <paul.burton@imgtec.com>		2016-09-21 15:04:04 +02:00
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cpu	MIPS: Ensure Config.K0=2 applies before any memory accesses	2016-09-21 15:04:04 +02:00
dts	mips: xilfpga: Add device tree files	2016-09-21 14:55:14 +02:00
include/asm	MIPS: Join the coherent domain when a CM is present	2016-09-21 15:04:04 +02:00
lib	MIPS: Ensure cache ops complete in mips_cache_reset	2016-09-21 15:04:04 +02:00
mach-ath79	MIPS: ath79: Use mach_cpu_init instead of arch_cpu_init	2016-09-21 15:04:04 +02:00
mach-au1x00	net: mii: Use spatch to update miiphy_register	2016-08-15 15:26:33 -05:00
mach-pic32	clk: convert API to match reset/mailbox style	2016-06-19 17:05:55 -06:00
config.mk	MIPS: provide a default u-boot-spl.lds	2016-05-31 09:38:11 +02:00
Kconfig	MIPS: Malta: Enable CM & L2 support	2016-09-21 15:04:04 +02:00
Makefile	MIPS: add tune for MIPS 34kc	2016-05-31 09:38:11 +02:00