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According PL310 TRM, Auxiliary Control Register " The register must be written to using a secure access, and it can be read using either a secure or a NS access. If you write to this register with a NS access, it results in a write response with a DECERR response, and the register is not updated. Writing to this register with the L2 cache enabled, that is, bit[0] of L2 Control Register set to 1, results in a SLVERR. " So If L2 cache is already enabled by ROM, chaning value of ACR will cause SLVERR and uboot hang. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> |
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| .. | ||
| cache.c | ||
| cmd_bmode.c | ||
| cmd_dek.c | ||
| cmd_hdmidet.c | ||
| cpu.c | ||
| ddrmc-vf610.c | ||
| hab.c | ||
| i2c-mxv7.c | ||
| imx_bootaux.c | ||
| init.c | ||
| iomux-v3.c | ||
| Kconfig | ||
| Makefile | ||
| misc.c | ||
| rdc-sema.c | ||
| sata.c | ||
| speed.c | ||
| spl.c | ||
| spl_sd.cfg | ||
| syscounter.c | ||
| timer.c | ||
| video.c | ||