Lokesh Vutla 802bb57a58 ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value ... The value in SDRAM_REF_CTRL controls the delay time between the initial rising edge of DDR_RESETn to rising edge of DDR_CKE (JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL should be written with a value corresponding to 500us delay before starting DDR initialization sequence, and configure proper value at the end of sequence. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>		2015-02-16 12:41:40 -05:00
..
asm	ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value	2015-02-16 12:41:40 -05:00
debug	arm: debug: replace license blocks with SPDX	2014-10-26 22:22:09 +01:00