Daniel Schwierzeck 6cb461b4f1 MIPS: fix endianess handling ... Make endianess of target CPU configurable. Use the new config option for dbau1550_el and pb1000 boards. Adapt linking of standalone applications to pass through endianess options to LD. Build tested with: - ELDK 4 mips_4KC- and mips4KCle - Sourcery CodeBench Lite 2011.03-93 With this patch all 26 MIPS boards can be compiled now in one step by running "MAKEALL -a mips". Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>		2012-04-02 15:54:53 +02:00
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au1x00	usb: replace wait_ms() with mdelay()	2012-03-19 00:08:16 +01:00
incaip	MIPS: IncaIP: Move all IncaIP specific code to separate subdirectory	2011-04-02 22:07:12 +09:00
cache.S	MIPS: fix inconsistency in config option for cache operation mode	2012-04-02 15:54:53 +02:00
config.mk	MIPS: fix endianess handling	2012-04-02 15:54:53 +02:00
cpu.c	MIPS: mips32: fix wrong loop bound in flush_cache()	2011-09-03 10:43:45 +09:00
interrupts.c	MIPS: Move content of arch/mips/cpu to arch/mips/cpu/mips32	2011-04-02 22:07:12 +09:00
Makefile	MIPS: Move timer code to arch/mips/cpu/$(CPU)/	2011-05-10 00:12:31 +09:00
start.S	MIPS: make cache operation mode configurable	2011-07-31 23:26:41 +09:00
time.c	Timer: Remove reset_timer() for non-Nios2 arches	2011-07-26 14:53:30 +02:00