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ARCv2 cores may have built-in SLC (System Level Cache, AKA L2-cache). This change adds functions required for controlling SLC: * slc_enable/disable * slc_flush/invalidate For now we just disable SLC to escape DMA coherency issues until either: * SLC flush/invalidate is supported in DMA APIin U-Boot * hardware DMA coherency is implemented (that might be board specific so probably we'll need to have a separate Kconfig option for controlling SLC explicitly) Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> |
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| .. | ||
| _millicodethunk.S | ||
| bootm.c | ||
| cache.c | ||
| cpu.c | ||
| init_helpers.c | ||
| interrupts.c | ||
| ints_low.S | ||
| libgcc2.c | ||
| libgcc2.h | ||
| Makefile | ||
| memcmp.S | ||
| memcpy-700.S | ||
| memset.S | ||
| relocate.c | ||
| reset.c | ||
| sections.c | ||
| start.S | ||
| strchr-700.S | ||
| strcmp.S | ||
| strcpy-700.S | ||
| strlen.S | ||
| timer.c | ||