Rajeshwari Shinde 6071bcaec1 EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0 ... MPLL clock-out of Exynos5250 Rev 1.0 is always at 1.6GHz. Adjust the divisor value to get 800MHz as needed by devices like UART etc Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>		2012-09-01 14:58:23 +02:00
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asm	EXYNOS5: CLOCK: Modify MPLL clock out for Exynos5250 Rev 1.0	2012-09-01 14:58:23 +02:00