Bin Meng 9c7dea602e x86: Refactor PIRQ routing support ... PIRQ routing is pretty much common in Intel chipset. It has several PIRQ links (normally 8) and corresponding registers (either in PCI configuration space or memory-mapped IBASE) to configure the legacy 8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing support using device tree and move it to a common place, so that we can easily add PIRQ routing support on a new platform. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>		2015-06-04 02:39:39 -06:00
..
clock	ARM: tegra: Add Tegra30 PCIe device tree node	2014-12-18 13:19:21 -07:00
dma	sunxi: dts: Sync all dts files with upstream kernel	2015-05-04 16:51:54 +02:00
gpio	tegra: dts: Bring in GPIO bindings from linux	2014-06-20 11:56:33 -06:00
input	dm: sunxi: dts: Add sun7i device tree files	2014-11-05 13:09:58 +01:00
interrupt-controller	tegra: dts: Bring in GPIO bindings from linux	2014-06-20 11:56:33 -06:00
interrupt-router	x86: Refactor PIRQ routing support	2015-06-04 02:39:39 -06:00
mrc	dt-bindings: Add Intel Quark MRC bindings	2015-02-06 12:07:44 -07:00
pinctrl	sunxi: dts: Sync all dts files with upstream kernel	2015-05-04 16:51:54 +02:00
pmic	sandbox: dts: add sandbox_pmic.dtsi and include it to sandbox.dts and test.dts	2015-05-14 19:59:21 -06:00
reset	arm: socfpga: dts: altr,rst-mgr.h: Move to SPDX license identifiers	2014-12-06 13:52:47 +01:00
thermal	sunxi: dts: Sync all dts files with upstream kernel	2015-05-04 16:51:54 +02:00