mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
2230d5482d
Fixed warnings for both ipq807x and ipq40xx builds. Change-Id: I69accebf525ee52f470335a14474378f5e7f65b0 Signed-off-by: Saravanan Jaganathan <sjaganat@codeaurora.org>
120 lines
3.5 KiB
C
120 lines
3.5 KiB
C
/*
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* Copyright (c) 2014 The Linux Foundation. All rights reserved.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef ___QCA_MMC_H_
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#define ___QCA_MMC_H_
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#define MMCIPOWER 0x000
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#define MCI_PWR_OFF 0x00
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#define MCI_PWR_UP 0x02
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#define MCI_PWR_ON 0x03
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#define MCI_SW_RST (1 << 7)
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#define MMCICLOCK 0x004
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#define MCI_CLK_ENABLE (1 << 8)
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#define MCI_CLK_PWRSAVE (1 << 9)
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#define MCI_CLK_FLOWENA (1 << 12)
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#define MCI_CLK_SELECTIN (1 << 15)
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#define MCI_CLK_WIDEBUS_1 (0 << 10)
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#define MCI_CLK_WIDEBUS_4 (2 << 10)
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#define MCI_CLK_WIDEBUS_8 (3 << 10)
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#define MMCIARGUMENT 0x008
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#define MMCICOMMAND 0x00c
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#define MCI_CPSM_RESPONSE (1 << 6)
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#define MCI_CPSM_LONGRSP (1 << 7)
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#define MCI_CPSM_ENABLE (1 << 10)
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#define MCI_CPSM_PROGENA (1 << 11)
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#define MMCIRESPCMD 0x010
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#define MMCIRESPONSE0 0x014
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#define MMCIRESPONSE1 0x018
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#define MMCIRESPONSE2 0x01c
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#define MMCIRESPONSE3 0x020
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#define MMCIDATATIMER 0x024
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#define MMCIDATALENGTH 0x028
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#define MMCIDATACTRL 0x02c
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#define MCI_DPSM_ENABLE (1 << 0)
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#define MCI_DPSM_DIRECTION (1 << 1)
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#define MCI_RX_DATA_PEND (1 << 20)
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#define MMCIDATACNT 0x030
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#define MMCISTATUS 0x034
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#define MCI_CMDCRCFAIL (1 << 0)
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#define MCI_DATACRCFAIL (1 << 1)
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#define MCI_CMDTIMEOUT (1 << 2)
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#define MCI_DATATIMEOUT (1 << 3)
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#define MCI_TXUNDERRUN (1 << 4)
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#define MCI_RXOVERRUN (1 << 5)
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#define MCI_CMDRESPEND (1 << 6)
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#define MCI_CMDSENT (1 << 7)
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#define MCI_DATAEND (1 << 8)
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#define MCI_DATABLOCKEND (1 << 10)
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#define MCI_CMDACTIVE (1 << 11)
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#define MCI_TXACTIVE (1 << 12)
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#define MCI_RXACTIVE (1 << 13)
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#define MCI_TXFIFOHALFEMPTY (1 << 14)
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#define MCI_RXFIFOHALFFULL (1 << 15)
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#define MCI_TXFIFOFULL (1 << 16)
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#define MCI_RXFIFOFULL (1 << 17)
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#define MCI_TXFIFOEMPTY (1 << 18)
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#define MCI_RXFIFOEMPTY (1 << 19)
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#define MCI_TXDATAAVLBL (1 << 20)
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#define MCI_RXDATAAVLBL (1 << 21)
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#define MMCICLEAR 0x038
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#define MCI_CMDCRCFAILCLR (1 << 0)
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#define MCI_DATACRCFAILCLR (1 << 1)
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#define MCI_CMDTIMEOUTCLR (1 << 2)
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#define MCI_DATATIMEOUTCLR (1 << 3)
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#define MCI_TXUNDERRUNCLR (1 << 4)
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#define MCI_RXOVERRUNCLR (1 << 5)
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#define MCI_CMDRESPENDCLR (1 << 6)
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#define MCI_CMDSENTCLR (1 << 7)
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#define MCI_DATAENDCLR (1 << 8)
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#define MCI_STARTBITERRCLR (1 << 9)
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#define MCI_DATABLOCKENDCLR (1 << 10)
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#define MCI_SDIOINTRCLR (1 << 22)
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#define MCI_PROGDONECLR (1 << 23)
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#define MCI_ATACMDCOMPLCLR (1 << 24)
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#define MCI_SDIOINTROPECLR (1 << 25)
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#define MCI_CCSTIMEOUTCLR (1 << 26)
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#define MCI_CLEAR_STATIC_MASK \
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(MCI_CMDCRCFAILCLR|MCI_DATACRCFAILCLR|MCI_CMDTIMEOUTCLR|\
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MCI_DATATIMEOUTCLR|MCI_TXUNDERRUNCLR|MCI_RXOVERRUNCLR| \
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MCI_CMDRESPENDCLR|MCI_CMDSENTCLR|MCI_DATAENDCLR| \
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MCI_STARTBITERRCLR|MCI_DATABLOCKENDCLR|MCI_SDIOINTRCLR| \
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MCI_SDIOINTROPECLR|MCI_PROGDONECLR|MCI_ATACMDCOMPLCLR| \
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MCI_CCSTIMEOUTCLR)
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#define MCI_STATUS2 0x06C
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#define MCI_MCLK_REG_WR_ACTIVE (1 << 0)
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#define MMCIFIFO 0x080 /* to 0x0bc */
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/*
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* The size of the FIFO in bytes.
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*/
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#define MCI_FIFOSIZE (16*4)
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#define MCI_FIFOHALFSIZE (MCI_FIFOSIZE / 2)
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#define MCI_FIFODEPTH 16
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#define MCI_HFIFO_COUNT (MCI_FIFODEPTH / 2)
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extern void emmc_clock_config(int mode);
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#endif /* __QCA_MMC_H_ */
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