mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
4f520fbf29
Changes to use the C Flags pushed by the openwrt package directly from within the qca953x target sources is done. Change-Id: Ib66cdf88ccef33e7805cc7a6831200502d7f1c23 Signed-off-by: Prabhu Jayakumar <pjayak@codeaurora.org>
202 lines
5.8 KiB
C
202 lines
5.8 KiB
C
#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
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#define CONFIG_BOOTDELAY 2 /* autoboot after 4 seconds */
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#define CONFIG_TIMESTAMP /* Print image info with timestamp */
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/*
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* Console I/O configuration
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*/
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {115200}
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/* Console I/O Buffer Size */
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#define CONFIG_SYS_CBSIZE 512
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "hush>"
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/*
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* FLASH and environment organization
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*/
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#ifndef FLASH_SIZE
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#define FLASH_SIZE 16
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#endif
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/*-----------------------------------------------------------------------
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* FLASH and environment organization
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#if (FLASH_SIZE == 32)
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#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
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#define ATH_MTDPARTS_MIB0 "64k(mib0)"
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#define ATH_ROOTFS_SIZE "14528k(rootfs)"
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#elif (FLASH_SIZE == 16)
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#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
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#define ATH_MTDPARTS_MIB0 "64k(mib0)"
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#define ATH_ROOTFS_SIZE "14528k(rootfs)"
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#elif (FLASH_SIZE == 8)
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#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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#define ATH_MTDPARTS_MIB0 "64k(mib0)"
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#define ATH_ROOTFS_SIZE "6336k(rootfs)"
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#elif (FLASH_SIZE == 1/2)
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#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
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#else
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#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
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#define ATH_MTDPARTS_MIB0 "64k(mib0)"
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#define ATH_ROOTFS_SIZE "6336k(rootfs)"
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#endif
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#define CFG_FLASH_SECTOR_SIZE (64*1024)
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#if (FLASH_SIZE == 32)
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#define CFG_FLASH_SIZE 0x02000000 /* Total flash size */
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#elif (FLASH_SIZE == 16)
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#define CFG_FLASH_SIZE 0x01000000 /* Total flash size */
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#elif (FLASH_SIZE == 8)
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#define CFG_FLASH_SIZE 0x00800000 /* max number of sectors on one chip */
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#elif (FLASH_SIZE == 1/2)
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#define CFG_FLASH_SIZE 0x00080000 /* Total flash size */
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#else
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#define CFG_FLASH_SIZE 0x00400000 /* Total flash size */
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#endif
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#ifndef COMPRESSED_UBOOT
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#define ENABLE_DYNAMIC_CONF 1
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#endif
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#undef CFG_ATHRS26_PHY
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#if (CFG_MAX_FLASH_SECT * CFG_FLASH_SECTOR_SIZE) != CFG_FLASH_SIZE
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# error "Invalid flash configuration"
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#endif
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#define CFG_FLASH_WORD_SIZE unsigned short
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#if defined(CONFIG_ATH_NAND_BR) && defined(COMPRESSED_UBOOT)
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#define CFG_FLASH_BASE 0xa0100000
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#else
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/* NOR Flash start address */
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#define CFG_FLASH_BASE 0x9f000000
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#endif
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#ifdef COMPRESSED_UBOOT
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#define BOOTSTRAP_TEXT_BASE CFG_FLASH_BASE
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#define BOOTSTRAP_CFG_MONITOR_BASE BOOTSTRAP_TEXT_BASE
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#endif
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#define CONFIG_PCI_CONFIG_DATA_IN_OTP
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/*
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* Defines to change flash size on reboot
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*/
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#ifdef ENABLE_DYNAMIC_CONF
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#define CFG_DDR_MAGIC 0xaabacada
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#define CFG_DDR_MAGIC_F (UBOOT_ENV_SEC_START + CFG_FLASH_SECTOR_SIZE - 0x30)
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#define CFG_DDR_CONFIG_VAL_F *(volatile int *)(CFG_DDR_MAGIC_F + 4)
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#define CFG_DDR_CONFIG2_VAL_F *(volatile int *)(CFG_DDR_MAGIC_F + 8)
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#define CFG_DDR_EXT_MODE_VAL_F *(volatile int *)(CFG_DDR_MAGIC_F + 12)
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#endif
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/*
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** Parameters defining the location of the calibration/initialization
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** information for the two Merlin devices.
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** NOTE: **This will change with different flash configurations**
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*/
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#define BOARDCAL (CFG_FLASH_BASE + CFG_FLASH_SIZE - 0x10000)
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#define WLANCAL (BOARDCAL + 0x1000)
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#define ATHEROS_PRODUCT_ID 137
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#define CAL_SECTOR (CFG_MAX_FLASH_SECT - 1)
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/* For Merlin, both PCI, PCI-E interfaces are valid */
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#define ATH_ART_PCICFG_OFFSET 12
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/*
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* The following for ENV settings
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*/
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_FLASH_BASE 0x9f000000
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#define CONFIG_SYS_MAX_FLASH_SECT 256
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_SIZE CFG_FLASH_SECTOR_SIZE //CFG_ENV_SIZE
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#define CONFIG_ENV_ADDR 0x9f040000
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/* Timer Specific */
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#define CONFIG_SYS_MHZ 550
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/* Since the count is incremented every other tick, divide by 2 -- CFG_HZ*/
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#define CONFIG_SYS_MIPS_TIMER_FREQ ((CONFIG_SYS_MHZ * 1000000)/2)
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#define CFG_DDR_REFRESH_VAL 0x4138
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/*
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* The following #defines are needed to get flash environment right
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*/
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#define CONFIG_SYS_MONITOR_BASE 0x9f000000
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#define CONFIG_SYS_MONITOR_LEN (192 << 10)
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#define CONFIG_SYS_MALLOC_LEN (128*1024)
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#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
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/*
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 32
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#define CONFIG_SYS_ICACHE_SIZE 65536
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#define CONFIG_SYS_DCACHE_SIZE 32768
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#define CONFIG_PCI 1
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#define CONFIG_CMD_PCI
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#define CONFIG_PCI_SCAN_SHOW
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/*#define CONFIG_USB 1*/
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#if pll
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#define CFG_PLL_FREQ (pll)
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#else
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#define CFG_PLL_FREQ CFG_PLL_650_600_200
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#endif
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#define CONFIG_ATH_SOC 1
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#define CONFIG_ATHEROS 1
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#define CONFIG_MACH_QCA953x 1
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#define CFG_INIT_STACK_IN_SRAM 1
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#define __CONFIG_BOARD_NAME ap147
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#define CONFIG_BOARD_NAME "ap147"
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#define BUILD_VERSION "g36c341f-dirty-1"
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#define CFG_ATHRS27_PHY 1
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#define CFG_ATH_GMAC_NMACS 2
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#define BOARD_NAME "AP147"
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#define CONFIG_LAST_STAGE_INIT
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#define CONFIG_DISPLAY_BOARDINFO 1
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#define CONFIG_CUSTOM_BOARDINFO 1
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#define CONFIG_SYS_TEXT_BASE 0x9f000000
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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#define CONFIG_SYS_LOAD_ADDR 0x81000000
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/*
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* Cache lock for stack
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*/
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#define CONFIG_SYS_INIT_SP_OFFSET 0x1000
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#define CFG_INIT_SRAM_SP_OFFSET 0xbd001800
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/*
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* Image type
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*/
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#define CONFIG_LZMA 1
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#define CONFIG_IMAGE_FORMAT_LEGACY
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/*
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* ethernet environment
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*/
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#define CONFIG_SYS_RX_ETH_BUFFER 8
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#define CONFIG_TFTP_BLOCKSIZE 512
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#define CONFIG_MII 1
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#define CFG_CMD_MII 1
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#define CONFIG_COMMANDS 1
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