Shengzhou Liu 5fc62fe570 driver/ddr/fsl: Add workaround for erratum A-009801 ... The initial training for the DDRC may provide results that are not optimized. The workaround provides better read timing margins. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>		2016-05-17 09:26:53 -07:00
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altera	ddr: altera: Repair DQ window centering code	2016-04-20 11:28:45 +02:00
fsl	driver/ddr/fsl: Add workaround for erratum A-009801	2016-05-17 09:26:53 -07:00
marvell	Fix spelling of "occurred".	2016-05-02 18:37:09 -04:00
microchip	drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.	2016-02-01 22:14:01 +01:00