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9acde129cc
The Vitesse VSC8601 RGMII PHY has internal delay for both Rx and Tx clock lines. They are configured using 2 bits in extended register 0x17. Therefore CFG_VSC8601_SKEW_TX and CFG_VSC8601_SKEW_RX have been introduced with valid values 0-3 giving 0.0, 1.4,1.7 and 2.0ns delay. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Acked-by: Andy Fleming <afleming@freescale.com> Acked-by: Ben Warren <biggerbadderben@gmail.com> -- drivers/net/tsec.c | 6 ++++++ drivers/net/tsec.h | 3 +++ 2 files changed, 9 insertions(+), 0 deletions(-) |
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| bios_emulator | ||
| block | ||
| dma | ||
| hwmon | ||
| i2c | ||
| input | ||
| misc | ||
| mtd | ||
| net | ||
| pci | ||
| pcmcia | ||
| qe | ||
| rtc | ||
| serial | ||
| spi | ||
| usb | ||
| video | ||