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https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
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f861f51c46
Since commit 623d96e89aca6("imx: wdog: correct wcr register settings")
issuing a 'reset' command causes the system to hang.
Unlike i.MX and Vybrid, the watchdog controller on LS102x is big-endian.
This means that the watchdog on LS1021 has been working by accident as
it does not use the big-endian accessors in drivers/watchdog/imx_watchdog.c.
Commit 623d96e89aca6("imx: wdog: correct wcr register settings") only
revelead the endianness problem on LS102x.
In order to fix the reset hang, introduce a reset_cpu() implementation that
is specific for ls102x, which accesses the watchdog WCR register in big-endian
format. All that is required to reset LS102x is to clear the SRS bit.
This approach is a temporary workaround to avoid a regression for LS102x
in the 2015.10 release. The proper fix is to make the watchdog driver
endian-aware, so that it can work for i.MX, Vybrid and LS102x.
Reported-by: Sinan Akman <sinan@writeme.com>
Tested-by: Sinan Akman <sinan@writeme.com>
Reviewed-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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| .. | ||
| clock.c | ||
| cpu.c | ||
| fdt.c | ||
| fsl_epu.c | ||
| fsl_epu.h | ||
| fsl_ls1_serdes.c | ||
| fsl_ls1_serdes.h | ||
| ls102xa_serdes.c | ||
| Makefile | ||
| psci.S | ||
| spl.c | ||
| timer.c | ||