mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
97c3087906
As the U-boot source is going to be common between ARM and MIPS architecture , it is required to pick only the files specific to the respective architectures during the build. So, move the qca arm target specific common files to another sub level by specifying the ARCH arm. Change-Id: I06b538834109981f21fef6270bfb8e437a2f5a7e Signed-off-by: Prabhu Jayakumar <pjayak@codeaurora.org>
450 lines
20 KiB
C
450 lines
20 KiB
C
/*
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* Copyright (c) 2012, 2015-2017 The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef QCA_NAND_H
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#define QCA_NAND_H
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#define IPQ806x_EBI2ND_BASE (0x1ac00000)
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#define IPQ40xx_EBI2ND_BASE (0x079b0000)
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#define IPQ40xx_QPIC_BAM_CTRL (0x07984000)
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struct ebi2nd_regs {
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uint32_t flash_cmd; /* 0x00000000 */
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uint32_t addr0; /* 0x00000004 */
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uint32_t addr1; /* 0x00000008 */
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uint32_t flash_chip_select; /* 0x0000000C */
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uint32_t exec_cmd; /* 0x00000010 */
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uint32_t flash_status; /* 0x00000014 */
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uint32_t buffer_status; /* 0x00000018 */
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uint32_t sflashc_status; /* 0x0000001C */
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uint32_t dev0_cfg0; /* 0x00000020 */
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uint32_t dev0_cfg1; /* 0x00000024 */
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uint32_t dev0_ecc_cfg; /* 0x00000028 */
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uint32_t dev1_ecc_cfg; /* 0x0000002C */
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uint32_t dev1_cfg0; /* 0x00000030 */
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uint32_t dev1_cfg1; /* 0x00000034 */
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uint32_t sflashc_cmd; /* 0x00000038 */
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uint32_t sflashc_exec_cmd; /* 0x0000003C */
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uint32_t flash_read_id; /* 0x00000040 */
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uint32_t flash_read_status; /* 0x00000044 */
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uint32_t flash_read_id2; /* 0x00000048 */
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uint8_t reserved0[4];
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uint32_t flash_config_data; /* 0x00000050 */
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uint32_t flash_config; /* 0x00000054 */
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uint32_t flash_config_mode; /* 0x00000058 */
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uint8_t reserved1[4];
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uint32_t flash_config_status; /* 0x00000060 */
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uint32_t macro1_reg; /* 0x00000064 */
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uint32_t hsddr_nand_cfg; /* 0x00000068 */
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uint8_t reserved2[4];
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uint32_t xfr_step1; /* 0x00000070 */
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uint32_t xfr_step2; /* 0x00000074 */
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uint32_t xfr_step3; /* 0x00000078 */
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uint32_t xfr_step4; /* 0x0000007C */
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uint32_t xfr_step5; /* 0x00000080 */
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uint32_t xfr_step6; /* 0x00000084 */
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uint32_t xfr_step7; /* 0x00000088 */
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uint8_t reserved3[4];
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uint32_t genp_reg0; /* 0x00000090 */
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uint32_t genp_reg1; /* 0x00000094 */
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uint32_t genp_reg2; /* 0x00000098 */
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uint32_t genp_reg3; /* 0x0000009C */
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uint32_t dev_cmd0; /* 0x000000A0 */
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uint32_t dev_cmd1; /* 0x000000A4 */
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uint32_t dev_cmd2; /* 0x000000A8 */
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uint32_t dev_cmd_vld; /* 0x000000AC */
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uint8_t reserved4[16];
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uint32_t addr2; /* 0x000000C0 */
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uint32_t addr3; /* 0x000000C4 */
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uint32_t addr4; /* 0x000000C8 */
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uint32_t addr5; /* 0x000000CC */
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uint32_t dev_cmd3; /* 0x000000D0 */
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uint32_t dev_cmd4; /* 0x000000D4 */
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uint32_t dev_cmd5; /* 0x000000D8 */
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uint32_t dev_cmd6; /* 0x000000DC */
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uint32_t sflashc_burst_cfg; /* 0x000000E0 */
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uint32_t addr6; /* 0x000000E4 */
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uint32_t erased_cw_detect_cfg; /* 0x000000E8 */
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uint32_t erased_cw_detect_status; /* 0x000000EC */
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uint32_t ebi2_ecc_buf_cfg; /* 0x000000F0 */
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uint32_t dbg_cfg; /* 0x000000F4 */
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uint32_t hw_profile_cfg; /* 0x000000F8 */
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uint32_t hw_info; /* 0x000000FC */
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uint32_t buffn_acc[144]; /* 0x00000100 */
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uint8_t reserved5[3008]; /* 0x00000340 */
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uint32_t qpic_nand_ctrl; /* 0x00000f00 */
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uint32_t qpic_nand_status; /* 0x00000f04 */
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uint32_t qpic_nand_version; /* 0x00000f08 */
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uint32_t qpic_nand_debug; /* 0x00000f0c */
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uint32_t qpic_irq_stts; /* 0x00000f10 */
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uint32_t qpic_irq_clr; /* 0x00000f14 */
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uint32_t qpic_irq_en; /* 0x00000f18 */
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uint32_t qpic_nand_mutex; /* 0x00000f1c */
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uint32_t qpic_nand_read_location_0; /* 0x00000f20 */
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uint32_t qpic_nand_read_location_1; /* 0x00000f24 */
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uint32_t qpic_nand_read_location_2; /* 0x00000f28 */
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uint32_t qpic_nand_read_location_3; /* 0x00000f2c */
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uint32_t qpic_nand_read_location_4; /* 0x00000f30 */
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uint8_t reserved6[12]; /* 0x00000f34 */
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uint32_t qpic_nand_config_bits; /* 0x00000f40 */
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uint32_t qpic_nand_mpu_bypass; /* 0x00000f44 */
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};
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#define QCA_NAND_IPQ 0
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#define QCA_NAND_QPIC 1
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/* Register: NAND_DEVn_CFG0 */
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#define SET_RD_MODE_AFTER_STATUS_MASK 0x80000000
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#define SET_RD_MODE_AFTER_STATUS_SEND_READ_CMD 0x80000000
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#define SET_RD_MODE_AFTER_STATUS_DO_NOT_SEND 0x00000000
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#define SET_RD_MODE_AFTER_STATUS(i) ((i) << 31)
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#define STATUS_BFR_READ_MASK 0x40000000
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#define STATUS_BFR_READ_DO_NOT_READ_STATUS 0x00000000
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#define STATUS_BFR_READ_READ_STATUS_BEFORE_DATA 0x40000000
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#define STATUS_BFR_READ(i) ((i) << 30)
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#define NUM_ADDR_CYCLES_MASK 0x38000000
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#define NUM_ADDR_CYCLES_NO_ADDRESS_CYCLES 0x00000000
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#define NUM_ADDR_CYCLES(i) ((i) << 27)
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#define SPARE_SIZE_BYTES_MASK 0x07800000
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#define SPARE_SIZE_BYTES(i) ((i) << 23)
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#define RS_ECC_PARITY_SIZE_BYTES_MASK 0x00780000
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#define RS_ECC_PARITY_SIZE_BYTES(i) ((i) << 19)
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#define UD_SIZE_BYTES_MASK 0x0007fe00
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#define UD_SIZE_BYTES(i) ((i) << 9)
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#define CW_PER_PAGE_MASK 0x000001c0
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#define CW_PER_PAGE_1_CODEWORD_PER_PAGE 0x00000000
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#define CW_PER_PAGE_2_CODEWORDS_PER_PAGE 0x00000040
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#define CW_PER_PAGE_3_CODEWORDS_PER_PAGE 0x00000080
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#define CW_PER_PAGE_4_CODEWORDS_PER_PAGE 0x000000C0
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#define CW_PER_PAGE_5_CODEWORDS_PER_PAGE 0x00000100
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#define CW_PER_PAGE_6_CODEWORDS_PER_PAGE 0x00000140
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#define CW_PER_PAGE_7_CODEWORDS_PER_PAGE 0x00000180
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#define CW_PER_PAGE_8_CODEWORDS_PER_PAGE 0x000001C0
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#define CW_PER_PAGE(i) ((i) << 6)
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#define MSB_CW_PER_PAGE_MASK 0x00000020
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#define MSB_CW_PER_PAGE(i) ((i) << 5)
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#define DISABLE_STATUS_AFTER_WRITE_MASK 0x00000010
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#define DISABLE_STATUS_AFTER_WRITE(i) ((i) << 4)
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#define BUSY_TIMEOUT_ERROR_SELECT_MASK 0x0000000f
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#define BUSY_TIMEOUT_ERROR_SELECT_16_MS 0x00000000
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#define BUSY_TIMEOUT_ERROR_SELECT_32_MS 0x00000001
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#define BUSY_TIMEOUT_ERROR_SELECT_64_MS 0x00000002
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#define BUSY_TIMEOUT_ERROR_SELECT_128_MS 0x00000003
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#define BUSY_TIMEOUT_ERROR_SELECT_256_MS 0x00000004
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#define BUSY_TIMEOUT_ERROR_SELECT_512_MS 0x00000005
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#define BUSY_TIMEOUT_ERROR_SELECT_1_SEC 0x00000006
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#define BUSY_TIMEOUT_ERROR_SELECT_2_SEC 0x00000007
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#define BUSY_TIMEOUT_ERROR_SELECT_1_MS 0x00000008
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#define BUSY_TIMEOUT_ERROR_SELECT(i) ((i) << 0)
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/* Register: NAND_DEVn_CFG1 */
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#define RS_ECC_MODE_MASK 0x30000000
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#define RS_ECC_MODE(i) ((i) << 28)
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#define ENABLE_BCH_ECC_MASK 0x08000000
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#define ENABLE_BCH_ECC_ENABLES_TAVOR_ECC_CORE_WITH_BCH_ENCODING_DECODING 0x08000000
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#define ENABLE_BCH_ECC(i) ((i) << 27)
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#define DISABLE_ECC_RESET_AFTER_OPDONE_MASK 0x02000000
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#define DISABLE_ECC_RESET_AFTER_OPDONE(i) ((i) << 25)
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#define ECC_DECODER_CGC_EN_MASK 0x01000000
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#define ECC_DECODER_CGC_EN_FREE_RUNNING_CLOCK 0x01000000
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#define ECC_DECODER_CGC_EN(i) ((i) << 24)
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#define ECC_ENCODER_CGC_EN_MASK 0x00800000
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#define ECC_ENCODER_CGC_EN_FREE_RUNNING_CLOCK 0x00800000
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#define ECC_ENCODER_CGC_EN(i) ((i) << 23)
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#define WR_RD_BSY_GAP_MASK 0x007e0000
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#define WR_RD_BSY_GAP_2_CLOCK_CYCLE_GAP 0x00000000
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#define WR_RD_BSY_GAP_4_CLOCK_CYCLES_GAP 0x00020000
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#define WR_RD_BSY_GAP_6_CLOCK_CYCLES_GAP 0x00040000
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#define WR_RD_BSY_GAP_8_CLOCK_CYCLES_GAP 0x00060000
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#define WR_RD_BSY_GAP_10_CLOCK_CYCLES_GAP 0x00080000
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#define WR_RD_BSY_GAP_128_CLOCK_CYCLES_GAP 0x007E0000
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#define WR_RD_BSY_GAP(i) ((i) << 17)
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#define BAD_BLOCK_IN_SPARE_AREA_MASK 0x00010000
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#define BAD_BLOCK_IN_SPARE_AREA_IN_USER_DATA_AREA 0x00000000
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#define BAD_BLOCK_IN_SPARE_AREA_IN_SPARE_AREA 0x00010000
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#define BAD_BLOCK_IN_SPARE_AREA(i) ((i) << 16)
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#define BAD_BLOCK_BYTE_NUM_MASK 0x0000ffc0
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#define BAD_BLOCK_BYTE_NUM(i) ((i) << 6)
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#define CS_ACTIVE_BSY_MASK 0x00000020
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#define CS_ACTIVE_BSY_ASSERT_CS_DURING_BUSY 0x00000020
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#define CS_ACTIVE_BSY_ALLOW_CS_DE_ASSERTION 0x00000000
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#define CS_ACTIVE_BSY(i) ((i) << 5)
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#define NAND_RECOVERY_CYCLES_MASK 0x0000001c
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#define NAND_RECOVERY_CYCLES_1_RECOVERY_CYCLE 0x00000000
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#define NAND_RECOVERY_CYCLES_2_RECOVERY_CYCLES 0x00000004
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#define NAND_RECOVERY_CYCLES_3_RECOVERY_CYCLES 0x00000008
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#define NAND_RECOVERY_CYCLES_8_RECOVERY_CYCLES 0x0000001C
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#define NAND_RECOVERY_CYCLES(i) ((i) << 2)
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#define WIDE_FLASH_MASK 0x00000002
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#define WIDE_FLASH_8_BIT_DATA_BUS 0x00000000
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#define WIDE_FLASH_16_BIT_DATA_BUS 0x00000002
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#define WIDE_FLASH(i) ((i) << 1)
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#define ECC_DISABLE_MASK 0x00000001
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#define ECC_DISABLE_ECC_ENABLED 0x00000000
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#define ECC_DISABLE_ECC_DISABLED 0x00000001
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#define ECC_DISABLE(i) ((i) << 0)
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/* Register: NAND_DEVn_ECC_CFG */
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#define ECC_FORCE_CLK_OPEN_MASK 0x40000000
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#define ECC_FORCE_CLK_OPEN(i) ((i) << 30)
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#define ECC_DEC_CLK_SHUTDOWN_MASK 0x20000000
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#define ECC_DEC_CLK_SHUTDOWN(i) ((i) << 29)
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#define ECC_ENC_CLK_SHUTDOWN_MASK 0x10000000
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#define ECC_ENC_CLK_SHUTDOWN(i) ((i) << 28)
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#define ECC_NUM_DATA_BYTES_MASK 0x03ff0000
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#define ECC_NUM_DATA_BYTES_516_BYTES 0x02040000
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#define ECC_NUM_DATA_BYTES_517_BYTES 0x02050000
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#define ECC_NUM_DATA_BYTES(i) ((i) << 16)
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#define BCH_ECC_PARITY_SIZE_BYTES_MASK 0x00001f00
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#define BCH_ECC_PARITY_SIZE_BYTES(i) ((i) << 8)
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#define BCH_ECC_MODE_MASK 0x00000030
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#define BCH_ECC_MODE_8_BIT_ECC_ERROR_DETECTION_CORRECTION 0x00000010
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#define BCH_ECC_MODE_12_BIT_ECC_ERROR_DETECTION_CORRECTION 0x00000020
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#define BCH_ECC_MODE_16_BIT_ECC_ERROR_DETECTION_CORRECTION 0x00000030
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#define BCH_ECC_MODE(i) ((i) << 4)
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#define ECC_SW_RESET_MASK 0x00000002
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#define ECC_SW_RESET_SOFTWARE_RESET_TO_ECC 0x00000002
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#define ECC_SW_RESET(i) ((i) << 1)
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#define BCH_ECC_DISABLE_MASK 0x00000001
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#define BCH_ECC_DISABLE_ECC_ENABLED 0x00000000
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#define BCH_ECC_DISABLE(i) ((i) << 0)
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/* Register: EBI2_ECC_BUF_CFG */
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#define NUM_STEPS_MASK 0x000003ff
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#define NUM_STEPS(i) ((i) << 0)
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/* Register: FLASH_DEV_CMD_VLD */
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#define SEQ_READ_START_VLD_MASK 0x00000010
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#define SEQ_READ_START_VLD(i) ((i) << 4)
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#define ERASE_START_VLD_MASK 0x00000008
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#define ERASE_START_VLD(i) ((i) << 3)
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#define WRITE_START_VLD_MASK 0x00000004
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#define WRITE_START_VLD(i) ((i) << 2)
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#define READ_STOP_VLD_MASK 0x00000002
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#define READ_STOP_VLD(i) ((i) << 1)
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#define READ_START_VLD_MASK 0x00000001
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#define READ_START_VLD(i) ((i) << 0)
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/* Register: NAND_ADDR0 */
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#define DEV_ADDR0_MASK 0xffffffff
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#define DEV_ADDR0(i) ((i) << 0)
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/* Register: NAND_ADDR1 */
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#define DEV_ADDR1_MASK 0xffffffff
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#define DEV_ADDR1(i) ((i) << 0)
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/* Register: NANDC_EXEC_CMD */
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#define EXEC_CMD_MASK 0x00000001
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#define EXEC_CMD_EXECUTE_THE_COMMAND 0x00000001
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#define EXEC_CMD(i) ((i) << 0)
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/* Register: NAND_ERASED_CW_DETECT_CFG */
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#define ERASED_CW_ECC_MASK_MASK 0x00000002
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#define ERASED_CW_ECC_MASK(i) ((i) << 1)
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#define AUTO_DETECT_RES_MASK 0x00000001
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#define AUTO_DETECT_RES(i) ((i) << 0)
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/* Register: NAND_ERASED_CW_DETECT_STATUS */
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#define PAGE_ERASED_MASK 0x00000020
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#define PAGE_ERASED(i) ((i) << 5)
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#define CODEWORD_ERASED_MASK 0x00000010
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#define CODEWORD_ERASED(i) ((i) << 4)
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#define ERASED_CW_ECC_MASK_MASK 0x00000002
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#define ERASED_CW_ECC_MASK(i) ((i) << 1)
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#define AUTO_DETECT_RES_MASK 0x00000001
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#define AUTO_DETECT_RES(i) ((i) << 0)
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/* Register: NAND_FLASH_CMD */
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#define ONE_NAND_INTR_STATUS_MASK 0x00040000
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#define ONE_NAND_INTR_STATUS(i) ((i) << 18)
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#define ONE_NAND_HOST_CFG_MASK 0x00020000
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#define ONE_NAND_HOST_CFG(i) ((i) << 17)
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#define AUTO_DETECT_DATA_XFR_SIZE_MASK 0x0001ff80
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#define AUTO_DETECT_DATA_XFR_SIZE(i) ((i) << 7)
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#define AUTO_DETECT_MASK 0x00000040
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#define AUTO_DETECT(i) ((i) << 6)
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#define LAST_PAGE_MASK 0x00000020
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#define LAST_PAGE(i) ((i) << 5)
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#define PAGE_ACC_MASK 0x00000010
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#define PAGE_ACC_PAGE_ACCESS_COMMAND 0x00000010
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#define PAGE_ACC_NON_PAGE_ACCESS_COMMAND 0x00000000
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#define PAGE_ACC(i) ((i) << 4)
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#define OP_CMD_MASK 0x0000000f
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#define OP_CMD_RESERVED_0 0x00000000
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#define OP_CMD_ABORT_TRANSACTION 0x00000001
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#define OP_CMD_PAGE_READ 0x00000002
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#define OP_CMD_PAGE_READ_WITH_ECC 0x00000003
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#define OP_CMD_PAGE_READ_WITH_ECC_SPARE 0x00000004
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#define OP_CMD_RESERVED_5 0x00000005
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#define OP_CMD_PROGRAM_PAGE 0x00000006
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#define OP_CMD_PAGE_PROGRAM_WITH_ECC 0x00000007
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#define OP_CMD_RESERVED_8 0x00000008
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#define OP_CMD_PROGRAM_PAGE_WITH_SPARE 0x00000009
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#define OP_CMD_BLOCK_ERASE 0x0000000A
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#define OP_CMD_FETCH_ID 0x0000000B
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#define OP_CMD_CHECK_STATUS 0x0000000C
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#define OP_CMD_RESET_NAND_FLASH_DEVICE 0x0000000D
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#define OP_CMD_RESERVED_E 0x0000000E
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#define OP_CMD_RESERVED_F 0x0000000F
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#define OP_CMD(i) ((i) << 0)
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/* Register: NAND_FLASH_STATUS */
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#define DEV_STATUS_MASK 0xffff0000
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#define DEV_STATUS(i) ((i) << 16)
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#define CODEWORD_CNTR_MASK 0x0000f000
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#define CODEWORD_CNTR(i) ((i) << 12)
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#define DEVICE_2KBYTE_MASK 0x00000800
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#define DEVICE_2KBYTE_2K_BYTE_PAGE_DEVICE 0x00000800
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#define DEVICE_2KBYTE_NOT_A_2K_BYTE_PAGE_DEVICE 0x00000000
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#define DEVICE_2KBYTE(i) ((i) << 11)
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#define DEVICE_512BYTE_MASK 0x00000400
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#define DEVICE_512BYTE_512_BYTE_PAGE_DEVICE 0x00000400
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#define DEVICE_512BYTE_NOT_A_512_BYTE_PAGE_DEVICE 0x00000000
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#define DEVICE_512BYTE(i) ((i) << 10)
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#define AUTO_DETECT_DONE_MASK 0x00000200
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#define AUTO_DETECT_DONE(i) ((i) << 9)
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#define MPU_ERROR_MASK 0x00000100
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#define MPU_ERROR_MPU_ERROR_FOR_THE_ACCESS 0x00000100
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#define MPU_ERROR_NO_ERROR 0x00000000
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#define MPU_ERROR(i) ((i) << 8)
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#define PROG_ERASE_OP_RESULT_MASK 0x00000080
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#define PROG_ERASE_OP_RESULT_SUCCESSFUL 0x00000000
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#define PROG_ERASE_OP_RESULT_NOT_SUCCESSFUL 0x00000080
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#define PROG_ERASE_OP_RESULT(i) ((i) << 7)
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#define NANDC_TIMEOUT_ERR_MASK 0x00000040
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#define NANDC_TIMEOUT_ERR_NO_ERROR 0x00000000
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#define NANDC_TIMEOUT_ERR_ERROR 0x00000040
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#define NANDC_TIMEOUT_ERR(i) ((i) << 6)
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#define READY_BSY_N_MASK 0x00000020
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#define READY_BSY_N_EXTERNAL_FLASH_IS_BUSY 0x00000000
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#define READY_BSY_N_EXTERNAL_FLASH_IS_READY 0x00000020
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#define READY_BSY_N(i) ((i) << 5)
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#define OP_ERR_MASK 0x00000010
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#define OP_ERR(i) ((i) << 4)
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#define OPER_STATUS_MASK 0x0000000f
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#define OPER_STATUS_IDLE_STATE 0x00000000
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#define OPER_STATUS_ABORT_TRANSACTION 0x00000001
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#define OPER_STATUS_PAGE_READ 0x00000002
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#define OPER_STATUS_PAGE_READ_WITH_ECC 0x00000003
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#define OPER_STATUS_PAGE_READ_WITH_ECC_AND_SPARE_DATA 0x00000004
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#define OPER_STATUS_SEQUENTIAL_PAGE_READ 0x00000005
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#define OPER_STATUS_PROGRAM_PAGE 0x00000006
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#define OPER_STATUS_PROGRAM_PAGE_WITH_ECC 0x00000007
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#define OPER_STATUS_RESERVED_PROGRAMMING 0x00000008
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#define OPER_STATUS_PROGRAM_PAGE_WITH_SPARE 0x00000009
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#define OPER_STATUS_BLOCK_ERASE 0x0000000A
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#define OPER_STATUS_FETCH_ID 0x0000000B
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#define OPER_STATUS_CHECK_STATUS 0x0000000C
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#define OPER_STATUS_RESET_FLASH_DEVICE 0x0000000D
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#define OPER_STATUS(i) ((i) << 0)
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/* Register: NANDC_BUFFER_STATUS */
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#define BAD_BLOCK_STATUS_MASK 0xffff0000
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#define BAD_BLOCK_STATUS(i) ((i) << 16)
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#define XFR_STEP2_REG_UPDATE_DONE_MASK 0x00000200
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#define XFR_STEP2_REG_UPDATE_DONE(i) ((i) << 9)
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#define UNCORRECTABLE_MASK 0x00000100
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#define UNCORRECTABLE(i) ((i) << 8)
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#define NUM_ERRORS_MASK 0x0000001f
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#define NUM_ERRORS(i) ((i) << 0)
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/* Register: FLASH_DEV_CMD1 */
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#define SEQ_READ_MODE_START_MASK 0xff000000
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#define SEQ_READ_MODE_START(i) ((i) << 24)
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#define SEQ_READ_MODE_ADDR_MASK 0x00ff0000
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#define SEQ_READ_MODE_ADDR(i) ((i) << 16)
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#define READ_START_MASK 0x0000ff00
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#define READ_START(i) ((i) << 8)
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#define READ_ADDR_MASK 0x000000ff
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#define READ_ADDR(i) ((i) << 0)
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/* Register: NAND_DEBUG */
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#define BAM_MODE_BIT_RESET (1 << 31)
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/* Register: NAND_CTRL */
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#define BAM_MODE_EN 0x1
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/* Register: BAM_CTRL */
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#define BAM_CTRL_CGC 0x00020000
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#endif
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