mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
97c3087906
As the U-boot source is going to be common between ARM and MIPS architecture , it is required to pick only the files specific to the respective architectures during the build. So, move the qca arm target specific common files to another sub level by specifying the ARCH arm. Change-Id: I06b538834109981f21fef6270bfb8e437a2f5a7e Signed-off-by: Prabhu Jayakumar <pjayak@codeaurora.org>
104 lines
4.6 KiB
C
104 lines
4.6 KiB
C
/*
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* Copyright (c) 2012, 2015-2017 The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef QCA_EBI2_H
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#define QCA_EBI2_H
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#define IPQ806x_EBI2CR_BASE (0x1A600000)
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#define IPQ40xx_EBI2CR_BASE (0x079a0000)
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struct ebi2cr_regs {
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uint32_t chip_select_cfg0; /* 0x00000000 */
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uint32_t cfg; /* 0x00000004 */
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uint32_t hw_info; /* 0x00000008 */
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uint8_t reserved0[20];
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uint32_t lcd_cfg0; /* 0x00000020 */
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uint32_t lcd_cfg1; /* 0x00000024 */
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uint8_t reserved1[8];
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uint32_t arbiter_cfg; /* 0x00000030 */
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uint8_t reserved2[28];
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uint32_t debug_sel; /* 0x00000050 */
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uint32_t crc_cfg; /* 0x00000054 */
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uint32_t crc_reminder_cfg; /* 0x00000058 */
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uint32_t nand_adm_mux; /* 0x0000005C */
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uint32_t mutex_addr_offset; /* 0x00000060 */
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uint32_t misr_value; /* 0x00000064 */
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uint32_t clkon_cfg; /* 0x00000068 */
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uint32_t core_clkon_cfg; /* 0x0000006C */
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uint8_t reserved3[144];
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/* QPIC */
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uint32_t qpic_qpic_version; /* 0x00000100 */
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uint32_t qpic_qpic_ctrl; /* 0x00000104 */
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uint32_t qpic_qpic_hwinfo; /* 0x00000108 */
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uint32_t qpic_qpic_reg_permission; /* 0x0000010C */
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uint32_t qpic_qpic_debug; /* 0x00000110 */
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};
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#define QPIC_EBI2CR_QPIC_LCDC_STTS 0x079A2014
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#define SW_RESET_DONE_SYNC (1 << 8)
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/* Register: EBI2_CHIP_SELECT_CFG0 */
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#define CS7_CFG_MASK 0x00001000
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#define CS7_CFG_DISABLE 0x00000000
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#define CS7_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00001000
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#define CS7_CFG(i) ((i) << 12)
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#define CS6_CFG_MASK 0x00000800
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#define CS6_CFG_DISABLE 0x00000000
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#define CS6_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000800
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#define CS6_CFG(i) ((i) << 11)
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#define ETM_CS_CFG_MASK 0x00000400
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#define ETM_CS_CFG_DISABLE 0x00000000
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#define ETM_CS_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000400
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#define ETM_CS_CFG(i) ((i) << 10)
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#define CS5_CFG_MASK 0x00000300
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#define CS5_CFG_DISABLE 0x00000000
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#define CS5_CFG_LCD_DEVICE_CONNECTED 0x00000100
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#define CS5_CFG_LCD_DEVICE_CHIP_ENABLE 0x00000200
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#define CS5_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000300
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#define CS5_CFG(i) ((i) << 8)
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#define CS4_CFG_MASK 0x000000c0
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#define CS4_CFG_DISABLE 0x00000000
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#define CS4_CFG_LCD_DEVICE_CONNECTED 0x00000040
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#define CS4_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x000000C0
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#define CS4_CFG(i) ((i) << 6)
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#define CS3_CFG_MASK 0x00000020
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#define CS3_CFG_DISABLE 0x00000000
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#define CS3_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000020
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#define CS3_CFG(i) ((i) << 5)
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#define CS2_CFG_MASK 0x00000010
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#define CS2_CFG_DISABLE 0x00000000
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#define CS2_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000010
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#define CS2_CFG(i) ((i) << 4)
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#define CS1_CFG_MASK 0x0000000c
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#define CS1_CFG_DISABLE 0x00000000
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#define CS1_CFG_SERIAL_FLASH_DEVICE 0x00000004
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#define CS1_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000008
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#define CS1_CFG(i) ((i) << 2)
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#define CS0_CFG_MASK 0x00000003
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#define CS0_CFG_DISABLE 0x00000000
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#define CS0_CFG_SERIAL_FLASH_DEVICE 0x00000001
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#define CS0_CFG_GENERAL_SRAM_MEMORY_INTERFACE 0x00000002
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#define CS0_CFG(i) ((i) << 0)
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/* Register: EBI2_CORE_CLKON_CFG */
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#define GATE_NAND_ENA (1 << 31)
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#define GATE_LCD_ENA (1 << 29)
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#endif
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