mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
425d52cd85
added boot type based nand or emmc flash selection. So machid based flash selection becomes obsolete. Change-Id: I96fa43d31d23397fa249e02f62b905d6e4e67770 Signed-off-by: Rajkumar Ayyasamy <quic_arajkuma@quicinc.com>
133 lines
3 KiB
Text
133 lines
3 KiB
Text
/*
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* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
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*
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/qcom/gpio-ipq5332.h>
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#include <dt-bindings/qcom/eth-ipq5332.h>
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/ {
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serial@78AF000 {
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compatible = "qca,ipq-uartdm";
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reg = <0x78af000 0x200>;
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m_value = <36>;
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n_value = <15625>;
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d_value = <15625>;
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bit_rate = <0xff>;
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status = "disabled";
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};
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timer {
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gcnt_cntcv_lo = <0x4a2000>;
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gcnt_cntcv_hi = <0x4a2004>;
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gpt_freq_hz = <24000000>;
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timer_load_val = <0x00FFFFFF 0xFFFFFFFF>;
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};
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spi {
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compatible = "qcom,spi-qup-v2.7.0";
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wr_pipe_0 = <4>;
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rd_pipe_0 = <5>;
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wr_pipe_1 = <6>;
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rd_pipe_1 = <7>;
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wr_pipe_2 = <8>;
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rd_pipe_2 = <9>;
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status = "ok";
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};
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nand: nand-controller@79B0000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,qpic-nand-v2.1.1";
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reg = <0x79B0000 0x10000>;
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status = "okay";
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};
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mmc: sdhci@7804000 {
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compatible = "qcom,sdhci-msm";
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status = "okay";
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};
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pci0: pci@20000000 {
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compatible = "qcom,ipq5332-pcie";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x20000000 0xf1d
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0x80000 0x3000
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0x20000F20 0xa8
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0x20001000 0x1000
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0x20300000 0xd00000
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0x20100000 0x100000
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0x1829000 0x60
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0x4B0000 0x800>;
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reg-names = "pci_dbi", "parf", "elbi","dm_iatu", "axi_bars",
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"axi_conf", "pci_rst", "pci_phy";
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gen3 = <1>;
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status = "disabled";
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skip_phy_int = <1>;
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};
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pci1: pci@18000000 {
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compatible = "qcom,ipq5332-pcie";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x18000000 0xf1d
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0x88000 0x3000
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0x18000F20 0xa8
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0x18001000 0x1000
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0x18300000 0xd00000
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0x18100000 0x100000
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0x1828000 0x60
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0x4B1000 0x1000>;
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reg-names = "pci_dbi", "parf", "elbi","dm_iatu", "axi_bars",
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"axi_conf", "pci_rst", "pci_phy";
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gen3 = <1>;
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status = "disabled";
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skip_phy_int = <1>;
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};
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pci2: pci@10000000 {
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compatible = "qcom,ipq5332-pcie";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x10000000 0xf1d
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0xF0000 0x3000
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0x10000F20 0xa8
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0x10001000 0x1000
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0x10300000 0xd00000
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0x10100000 0x100000
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0x182A000 0x60
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0x4B1800 0x800>;
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reg-names = "pci_dbi", "parf", "elbi","dm_iatu", "axi_bars",
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"axi_conf", "pci_rst", "pci_phy";
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gen3 = <1>;
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status = "disabled";
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skip_phy_int = <1>;
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};
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xhci@8a00000 {
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compatible = "qca,dwc3-ipq";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x8a00000 0xe000>;
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};
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i2c@78B6000 {
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compatible = "qcom,qup-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x78B6000 0x600>;
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clock-frequency = <400000>;
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};
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};
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