Priyanka Jain 32c8cfb23c fsl_esdhc: Deal with watermark level register related changes ... P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark level register description has been changed: 9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00 25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00 Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>		2011-04-10 11:17:55 -05:00
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asm	fsl_esdhc: Deal with watermark level register related changes	2011-04-10 11:17:55 -05:00