mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2026-03-11 11:38:51 +01:00
0f149a240a
Change TLV message buffer offsets to match with kernel that has been adjusted to use last 16K of memory allocated for crashdump buffer. This was done to accomodate greater number of dump segemnts. Change-Id: Idb8c1bab6a0900152a9d413382b2b3c87a19170e Signed-off-by: Venkat Raju Sana <vrsana@codeaurora.org>
378 lines
10 KiB
C
378 lines
10 KiB
C
/*
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* Copyright (c) 2012-2015 The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _IPQ806x_CDP_H
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#define _IPQ806x_CDP_H
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/*
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* Disabled for actual chip.
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* #define CONFIG_RUMI
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*/
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#if !defined(DO_DEPS_ONLY) || defined(DO_SOC_DEPS_ONLY)
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/*
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* Beat the system! tools/scripts/make-asm-offsets uses
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* the following hard-coded define for both u-boot's
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* ASM offsets and platform specific ASM offsets :(
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*/
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#include <generated/generic-asm-offsets.h>
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#ifdef __ASM_OFFSETS_H__
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#undef __ASM_OFFSETS_H__
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#endif
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#if !defined(DO_SOC_DEPS_ONLY)
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#include <generated/asm-offsets.h>
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#endif
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#endif /* !DO_DEPS_ONLY */
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#define CONFIG_IPQ806X
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#define CONFIG_IPQ_NO_RELOC
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#define CONFIG_SMP_CMD_SUPPORT
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#ifdef CONFIG_SMP_CMD_SUPPORT
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#define NR_CPUS 2
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#endif
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_SYS_CACHELINE_SIZE 64
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#define CONFIG_IPQ806X_ENV
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#define CONFIG_SYS_BOOTM_LEN (64 << 20)
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#define CONFIG_IPQ_FDT_HIGH 0xffffffff
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#define CONFIG_BOOTARGS "console=ttyMSM0,115200n8"
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_VSNPRINTF
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#define CONFIG_FIT_DISABLE_SHA256
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#define CONFIG_MBN_HEADER
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#define CONFIG_IPQ_APPSBL_IMG_TYPE 0x5
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#ifdef CONFIG_USB_XHCI_IPQ
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#define CONFIG_USB_XHCI
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#define CONFIG_USB_XHCI_DWC3
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#define CONFIG_CMD_USB
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#define CONFIG_DOS_PARTITION
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#define CONFIG_USB_STORAGE
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#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#endif
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#define CONFIG_IPQ806X_UART
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#undef CONFIG_CMD_FLASH
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#undef CONFIG_CMD_FPGA /* FPGA configuration support */
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#undef CONFIG_CMD_IMI
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#undef CONFIG_CMD_IMLS
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#undef CONFIG_CMD_NFS /* NFS support */
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#define CONFIG_CMD_NET /* network support */
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#define CONFIG_CMD_DHCP
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#undef CONFIG_SYS_MAX_FLASH_SECT
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_CMD_PING
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#define CONFIG_IPQ_SNPS_GMAC
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#define CONFIG_MII
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#define CONFIG_CMD_MII
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#define CONFIG_BITBANGMII
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#define CONFIG_BITBANGMII_MULTI
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#define CONFIG_IPQ_SWITCH_ATHRS17
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#define CONFIG_IPQ_SWITCH_QCA8511
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#define CONFIG_SYS_RX_ETH_BUFFER 8
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#define CONFIG_IPQ_NO_MACS 4
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#undef CONFIG_BOARD_EARLY_INIT_F
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#undef CONFIG_HW_WATCHDOG
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#define CONFIG_SYS_DEVICE_NULLDEV
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#define CONFIG_FLASH_PROTECT
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#define CONFIG_CMD_FLASHWRITE
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/* Environment */
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#define CONFIG_MSM_PCOMM
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_ENV_SIZE CONFIG_ENV_SIZE_MAX
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#define CONFIG_ENV_RANGE board_env_range
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#define CONFIG_ENV_SIZE_MAX (256 << 10) /* 256 KB */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE_MAX + (512 << 10))
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/*
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*Run command support
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*/
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#define CONFIG_CMD_RUN
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/*
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* select serial console configuration
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*/
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#define CONFIG_CONS_INDEX 1
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
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115200}
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#define V_PROMPT "(IPQ) # "
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#ifndef CONFIG_SYS_PROMPT
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#define CONFIG_SYS_PROMPT V_PROMPT
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#endif
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#define CONFIG_SYS_CBSIZE (512 * 2) /* Console I/O Buffer Size */
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - CONFIG_SYS_MALLOC_LEN - CONFIG_ENV_SIZE - GENERATED_BD_INFO_SIZE)
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_SDRAM_BASE 0x40000000
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#define CONFIG_SYS_TEXT_BASE 0x42000000
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#define CONFIG_SYS_SDRAM_SIZE 0x10000000
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#define CONFIG_MAX_RAM_BANK_SIZE CONFIG_SYS_SDRAM_SIZE
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (64 << 20))
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#define CONFIG_ROOTFS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (96 << 20))
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#define QCA_KERNEL_START_ADDR CONFIG_SYS_SDRAM_BASE
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#define QCA_BOOT_PARAMS_ADDR (QCA_KERNEL_START_ADDR + 0x100)
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#define CONFIG_QCA_SMEM_BASE CONFIG_SYS_SDRAM_BASE + 0x1000000
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#define CONFIG_OF_COMBINE 1
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#define CONFIG_CMD_BOOTZ
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/*
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* I2C Configs
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*/
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#ifdef CONFIG_IPQ806X_I2C
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#define CONFIG_SYS_I2C_QUP
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#define CONFIG_CMD_I2C
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#define CONFIG_DM_I2C
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#endif
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/*
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* PCI Configs
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*/
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#define PCI_MAX_DEVICES 3
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#ifdef CONFIG_PCI_IPQ
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#define CONFIG_PCI
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#define CONFIG_CMD_PCI
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#define CONFIG_PCI_SCAN_SHOW
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#endif
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/*
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* MMC Configs
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*/
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#define CONFIG_QCA_MMC
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#ifdef CONFIG_QCA_MMC
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#define CONFIG_CMD_MMC
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#define CONFIG_MMC
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#define CONFIG_EFI_PARTITION
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#define CONFIG_GENERIC_MMC
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#define CONFIG_ENV_IS_IN_MMC
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#endif
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#define QCA_ROOT_FS_PART_NAME "rootfs"
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/*
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* CRASH DUMP ENABLE
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*/
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#define CONFIG_QCA_APPSBL_DLOAD 1
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#ifdef CONFIG_QCA_APPSBL_DLOAD
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#define CONFIG_CMD_TFTPPUT
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/* We will be uploading very big files */
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#undef CONFIG_NET_RETRY_COUNT
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#define CONFIG_NET_RETRY_COUNT 500
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#endif
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#ifndef __ASSEMBLY__
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#include <compiler.h>
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/*
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* XXX XXX Please do not instantiate this structure. XXX XXX
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* This is just a convenience to avoid
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* - adding #defines for every new reservation
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* - updating the multiple associated defines like smem base,
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* kernel start etc...
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* - re-calculation of the defines if the order changes or
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* some reservations are deleted
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* For new reservations just adding a member to the structure should
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* suffice.
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* Ensure that the size of this structure matches with the definition
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* of the following IPQ806x compile time definitions
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* PHYS_OFFSET (linux-sources/arch/arm/mach-msm/Kconfig)
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* zreladdr (linux-sources/arch/arm/mach-msm/Makefile.boot)
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* CONFIG_SYS_INIT_SP_ADDR defined above should point to the bottom.
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* MSM_SHARED_RAM_PHYS (linux-sources/arch/arm/mach-msm/board-ipq806x.c)
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*
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*/
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extern loff_t board_env_offset;
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extern loff_t board_env_range;
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extern loff_t board_env_size;
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#if !defined(DO_DEPS_ONLY) || defined(DO_SOC_DEPS_ONLY)
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typedef struct {
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uint8_t nss[16 * 1024 * 1024];
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uint8_t smem[2 * 1024 * 1024];
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#ifdef CONFIG_QCA_APPSBL_DLOAD
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uint8_t uboot[1 * 1024 * 1024];
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uint8_t nsstcmdump[128 * 1024];
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uint8_t sbl3[384 * 1024];
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uint8_t plcfwdump[512*1024];
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uint8_t wlanfwdump[(1 * 1024 * 1024) - GENERATED_GBL_DATA_SIZE];
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uint8_t init_stack[GENERATED_GBL_DATA_SIZE];
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#endif
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} __attribute__ ((__packed__)) ipq_mem_reserve_t;
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/* Convenience macros for the above convenience structure :-) */
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#define IPQ_MEM_RESERVE_SIZE(x) sizeof(((ipq_mem_reserve_t *)0)->x)
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#define IPQ_MEM_RESERVE_BASE(x) \
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(CONFIG_SYS_SDRAM_BASE + \
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((uint32_t)&(((ipq_mem_reserve_t *)0)->x)))
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#endif
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#define IPQ_NSSTCM_DUMP_ADDR (IPQ_MEM_RESERVE_BASE(nsstcmdump))
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#define IPQ_TEMP_DUMP_ADDR (IPQ_MEM_RESERVE_BASE(nsstcmdump))
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#define IPQ_TFTP_MIN_ADDR (CONFIG_SYS_SDRAM_BASE + (64 << 20))
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#define IPQ_TFTP_MAX_ADDR (gd->bd->bi_dram[0].start + \
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gd->bd->bi_dram[0].size)
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#define CONFIG_QCA_SMEM_BASE CONFIG_SYS_SDRAM_BASE + 0x1000000
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#endif /* __ASSEMBLY__ */
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#ifndef CONFIG_FIT
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#define CONFIG_FIT
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#endif
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#define CONFIG_SYS_NULLDEV
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#define CONFIG_CMD_XIMG
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/*Support for Compressed DTB image*/
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#ifdef CONFIG_FIT
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#define CONFIG_DTB_COMPRESSION
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#define CONFIG_DTB_LOAD_MAXLEN 0x100000
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#endif
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/*
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* SPI Flash Configs
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*/
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#define CONFIG_QCA_SPI
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#define CONFIG_SPI_FLASH
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#define CONFIG_CMD_SF
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#define CONFIG_SPI_FLASH_STMICRO
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#define CONFIG_SPI_FLASH_SPANSION
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#define CONFIG_SPI_FLASH_MACRONIX
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#define CONFIG_SPI_FLASH_WINBOND
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#define CONFIG_ENV_IS_IN_SPI_FLASH 1
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#define CONFIG_ENV_SECT_SIZE (64 * 1024)
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#define CONFIG_SPI_FLASH_USE_4K_SECTORS
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#define CONFIG_SF_DEFAULT_BUS 0
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#define CONFIG_SF_DEFAULT_CS 0
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#define CONFIG_SF_DEFAULT_SPEED (48 * 1000 * 1000)
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
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#define CONFIG_SPI_FLASH_BAR
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/*
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*MTEST Configs
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*/
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x1300000
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#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + 0x100
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/*NAND Flash Configs*/
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#define CONFIG_CMD_NAND
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#define CONFIG_IPQ_NAND
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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#define CONFIG_SYS_NAND_SELF_INIT
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#define CONFIG_IPQ_MAX_SPI_DEVICE 1
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#define CONFIG_IPQ_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_MAX_NAND_DEVICE (CONFIG_IPQ_MAX_NAND_DEVICE + \
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CONFIG_IPQ_MAX_SPI_DEVICE)
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#define CONFIG_IPQ_NAND_NAND_INFO_IDX 0
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#define CONFIG_IPQ_SPI_NOR_INFO_IDX 1
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#define CONFIG_NAND_FLASH_INFO_IDX CONFIG_IPQ_NAND_NAND_INFO_IDX
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#define CONFIG_SPI_FLASH_INFO_IDX CONFIG_IPQ_SPI_NOR_INFO_IDX
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#define QCA_SPI_NOR_DEVICE "nand1"
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#define CONFIG_FDT_FIXUP_PARTITIONS
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#define NUM_ALT_PARTITION 8
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#define CONFIG_MTD_DEVICE
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#define CONFIG_MTD_PARTITIONS
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_BOOTDELAY 2
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#define CONFIG_BOOTCOMMAND "bootipq"
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#define CONFIG_BOARD_LATE_INIT
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#define CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_OFFSET board_env_offset
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/*for ubi*/
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#define CONFIG_CMD_UBI
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#define CONFIG_RBTREE
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#ifdef CONFIG_OF_BOARD_SETUP
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#define DLOAD_DISABLE 1
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#define BOOT_VERSION 0
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#define TZ_VERSION 1
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#endif
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/* L1 cache line size is 64 bytes, L2 cache line size is 128 bytes
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* Cache flush and invalidation based on L1 cache, so the cache line
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* size is configured to 64 */
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#define CONFIG_SYS_CACHELINE_SIZE 64
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#define CONFIG_CMD_CACHE
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/*#define CONFIG_SYS_DCACHE_OFF*/
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/* Enabling this flag will report any L2 errors.
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* By default we are disabling it */
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#define CONFIG_IPQ_REPORT_L2ERR
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/*
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* Location in IMEM which contains the physical address of
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* 4K page allocated from kernel for storing the crashdump data
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*/
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#define CONFIG_QCA_KERNEL_CRASHDUMP_ADDRESS *((unsigned int *)0x2A03F658)
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#define CONFIG_CPU_CONTEXT_DUMP_SIZE 2048
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#define TLV_BUF_OFFSET 2048
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#define CONFIG_TLV_DUMP_SIZE 2048
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#define SCM_CMD_TZ_CONFIG_HW_FOR_RAM_DUMP_ID 0xFFFFFFFF /* Invalid CMD ID */
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#define SCM_CMD_TZ_FORCE_DLOAD_ID 0xFFFFFFFF /* Invalid CMD ID */
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/*
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* CRASH DUMP ENABLE
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*/
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#define CONFIG_QCA_APPSBL_DLOAD 1
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#define TLMM_BASE_ADDR 0x00800000
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#define GPIO_CONFIG_ADDR(x) (TLMM_BASE_ADDR + 0x1000 + (x)*0x10)
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#define GPIO_IN_OUT_ADDR(x) (TLMM_BASE_ADDR + 0x1004 + (x)*0x10)
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#undef CONFIG_IPQ_ROOTFS_AUTH
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#endif /* _IPQ806x_CDP_H */
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