mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
2a8bb9d7d7
Change-Id: If83199c83275dba83350ddbf0f2d3a80de3e9c65 Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
440 lines
13 KiB
C
440 lines
13 KiB
C
/*
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* Copyright (c) 2008, Google Inc.
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* All rights reserved.
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* Copyright (c) 2009-2015, The Linux Foundation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef __QPIC_NAND_H
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#define __QPIC_NAND_H
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#if defined(CONFIG_IPQ40XX) || defined(CONFIG_IPQ_RUMI)
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#define QPIC_EBI2ND_BASE (0x079b0000)
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#else
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#error "QPIC NAND not supported"
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#endif
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#define QPIC_BAM_CTRL_BASE (0x07984000)
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#define NAND_REG(off) (QPIC_EBI2ND_BASE + (off))
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#define NAND_FLASH_CMD NAND_REG(0x0000)
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#define NAND_ADDR0 NAND_REG(0x0004)
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#define NAND_ADDR1 NAND_REG(0x0008)
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#define NAND_FLASH_CHIP_SELECT NAND_REG(0x000C)
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#define NAND_EXEC_CMD NAND_REG(0x0010)
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#define NAND_FLASH_STATUS NAND_REG(0x0014)
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#define NAND_BUFFER_STATUS NAND_REG(0x0018)
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#define NAND_DEV0_CFG0 NAND_REG(0x0020)
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#define NAND_DEV0_CFG1 NAND_REG(0x0024)
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#define NAND_DEV0_ECC_CFG NAND_REG(0x0028)
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#define NAND_DEV1_CFG0 NAND_REG(0x0030)
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#define NAND_DEV1_CFG1 NAND_REG(0x0034)
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#define NAND_SFLASHC_CMD NAND_REG(0x0038)
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#define NAND_SFLASHC_EXEC_CMD NAND_REG(0x003C)
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#define NAND_READ_ID NAND_REG(0x0040)
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#define NAND_READ_STATUS NAND_REG(0x0044)
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#define NAND_CONFIG_DATA NAND_REG(0x0050)
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#define NAND_CONFIG NAND_REG(0x0054)
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#define NAND_CONFIG_MODE NAND_REG(0x0058)
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#define NAND_CONFIG_STATUS NAND_REG(0x0060)
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#define NAND_MACRO1_REG NAND_REG(0x0064)
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#define NAND_XFR_STEP1 NAND_REG(0x0070)
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#define NAND_XFR_STEP2 NAND_REG(0x0074)
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#define NAND_XFR_STEP3 NAND_REG(0x0078)
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#define NAND_XFR_STEP4 NAND_REG(0x007C)
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#define NAND_XFR_STEP5 NAND_REG(0x0080)
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#define NAND_XFR_STEP6 NAND_REG(0x0084)
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#define NAND_XFR_STEP7 NAND_REG(0x0088)
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#define NAND_GENP_REG0 NAND_REG(0x0090)
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#define NAND_GENP_REG1 NAND_REG(0x0094)
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#define NAND_GENP_REG2 NAND_REG(0x0098)
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#define NAND_GENP_REG3 NAND_REG(0x009C)
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#define NAND_SFLASHC_STATUS NAND_REG(0x001C)
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#define NAND_DEV_CMD0 NAND_REG(0x00A0)
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#define NAND_DEV_CMD1_V1_4_20 NAND_REG(0x00A4)
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#define NAND_DEV_CMD2 NAND_REG(0x00A8)
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#define NAND_DEV_CMD_VLD_V1_4_20 NAND_REG(0x00AC)
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#define NAND_EBI2_MISR_SIG_REG NAND_REG(0x00B0)
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#define NAND_ADDR2 NAND_REG(0x00C0)
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#define NAND_ADDR3 NAND_REG(0x00C4)
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#define NAND_ADDR4 NAND_REG(0x00C8)
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#define NAND_ADDR5 NAND_REG(0x00CC)
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#define NAND_DEV_CMD3 NAND_REG(0x00D0)
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#define NAND_DEV_CMD4 NAND_REG(0x00D4)
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#define NAND_DEV_CMD5 NAND_REG(0x00D8)
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#define NAND_DEV_CMD6 NAND_REG(0x00DC)
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#define NAND_SFLASHC_BURST_CFG NAND_REG(0x00E0)
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#define NAND_ADDR6 NAND_REG(0x00E4)
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#define NAND_ERASED_CW_DETECT_CFG NAND_REG(0x00E8)
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#define NAND_ERASED_CW_DETECT_STATUS NAND_REG(0x00EC)
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#define NAND_EBI2_ECC_BUF_CFG NAND_REG(0x00F0)
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#define NAND_HW_INFO NAND_REG(0x00FC)
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#define NAND_FLASH_BUFFER NAND_REG(0x0100)
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#define QPIC_NAND_CTRL NAND_REG(0x0F00)
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#define QPIC_NAND_DEBUG NAND_REG(0x0F0C)
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/* NANDc registers used during BAM transfer */
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#define NAND_READ_LOCATION_n(n) (NAND_REG(0xF20) + 4 * (n))
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#define NAND_RD_LOC_LAST_BIT(x) ((x) << 31)
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#define NAND_RD_LOC_SIZE(x) ((x) << 16)
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#define NAND_RD_LOC_OFFSET(x) ((x) << 0)
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#define NAND_DEV_CMD_VLD_V1_5_20 NAND_REG(0x70AC)
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#define NAND_DEV_CMD1_V1_5_20 NAND_REG(0x70A4)
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/* Shift Values */
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#define NAND_DEV0_CFG1_WIDE_BUS_SHIFT 1
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#define NAND_DEV0_CFG0_DIS_STS_AFTER_WR_SHIFT 4
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#define NAND_DEV0_CFG0_CW_PER_PAGE_SHIFT 6
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#define NAND_DEV0_CFG0_UD_SIZE_BYTES_SHIFT 9
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#define NAND_DEV0_CFG0_ADDR_CYCLE_SHIFT 27
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#define NAND_DEV0_CFG0_SPARE_SZ_BYTES_SHIFT 23
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#define NAND_DEV0_CFG1_RECOVERY_CYCLES_SHIFT 2
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#define NAND_DEV0_CFG1_CS_ACTIVE_BSY_SHIFT 5
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#define NAND_DEV0_CFG1_BAD_BLK_BYTE_NUM_SHIFT 6
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#define NAND_DEV0_CFG1_BAD_BLK_IN_SPARE_SHIFT 16
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#define NAND_DEV0_CFG1_WR_RD_BSY_GAP_SHIFT 17
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#define NAND_DEV0_ECC_DISABLE_SHIFT 0
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#define NAND_DEV0_ECC_SW_RESET_SHIFT 1
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#define NAND_DEV0_ECC_MODE_SHIFT 4
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#define NAND_DEV0_ECC_DISABLE_SHIFT 0
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#define NAND_DEV0_ECC_PARITY_SZ_BYTES_SHIFT 8
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#define NAND_DEV0_ECC_NUM_DATA_BYTES 16
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#define NAND_DEV0_ECC_FORCE_CLK_OPEN_SHIFT 30
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#define NAND_ERASED_CW_DETECT_STATUS_PAGE_ALL_ERASED 7
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#define NAND_ERASED_CW_DETECT_STATUS_CODEWORD_ALL_ERASED 6
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#define NAND_ERASED_CW_DETECT_STATUS_CODEWORD_ERASED 4
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#define NAND_ERASED_CW_DETECT_CFG_RESET_CTRL 1
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#define NAND_ERASED_CW_DETECT_CFG_ACTIVATE_CTRL 0
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#define NAND_ERASED_CW_DETECT_ERASED_CW_ECC_MASK (1 << 1)
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#define NAND_ERASED_CW_DETECT_ERASED_CW_ECC_NO_MASK (0 << 1)
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/* device commands */
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#define NAND_CMD_SOFT_RESET 0x01
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#define NAND_CMD_PAGE_READ 0x32
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#define NAND_CMD_PAGE_READ_ECC 0x33
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#define NAND_CMD_PAGE_READ_ALL 0x34
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#define NAND_CMD_SEQ_PAGE_READ 0x15
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#define NAND_CMD_PRG_PAGE 0x36
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#define NAND_CMD_PRG_PAGE_ECC 0x37
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#define NAND_CMD_PRG_PAGE_ALL 0x39
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#define NAND_CMD_BLOCK_ERASE 0x3A
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#define NAND_CMD_FETCH_ID 0x0B
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/* NAND Status errors */
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#define NAND_FLASH_MPU_ERR (1 << 8)
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#define NAND_FLASH_TIMEOUT_ERR (1 << 6)
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#define NAND_FLASH_OP_ERR (1 << 4)
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#define NAND_FLASH_ERR (NAND_FLASH_MPU_ERR | \
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NAND_FLASH_TIMEOUT_ERR | \
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NAND_FLASH_OP_ERR)
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#define PROG_ERASE_OP_RESULT (1 << 7)
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#define NUM_ERRORS_MASK 0x0000001f
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#define NUM_ERRORS(i) ((i) << 0)
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#define DATA_CONSUMER_PIPE_INDEX 0
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#define DATA_PRODUCER_PIPE_INDEX 1
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#define CMD_PIPE_INDEX 2
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/* Define BAM pipe lock groups for NANDc*/
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#define P_LOCK_GROUP_0 0
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/* Define BAM pipe lock super groups for NANDc
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* Note: This is configured by TZ.
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*/
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#define P_LOCK_SUPERGROUP_0 0
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#define P_LOCK_SUPERGROUP_1 1
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#define ONFI_SIGNATURE 0x49464E4F
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#define ONFI_CRC_POLYNOMIAL 0x8005
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#define ONFI_CRC_INIT_VALUE 0x4F4E
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#define ONFI_READ_PARAM_PAGE_ADDR_CYCLES 1
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#define ONFI_READ_ID_ADDR_CYCLES 1
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#define ONFI_READ_ID_CMD 0x90
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#define ONFI_READ_PARAM_PAGE_CMD 0xEC
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#define ONFI_READ_ID_ADDR 0x20
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#define ONFI_READ_PARAM_PAGE_ADDR 0x00
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#define NAND_CFG0_RAW_ONFI_ID 0x88000800
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#define NAND_CFG0_RAW_ONFI_PARAM_PAGE 0x88040000
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#define NAND_CFG1_RAW_ONFI_ID 0x0005045D
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#define NAND_CFG1_RAW_ONFI_PARAM_PAGE 0x0005045D
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#define NAND_CFG0 0x290409c0
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#define NAND_CFG1 0x08045d5c
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#define NAND_ECC_BCH_CFG 0x42040d10
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#define NAND_Bad_Block 0x00000175
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#define NAND_ECC_BUF_CFG 0x00000203
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#define ONFI_READ_ID_BUFFER_SIZE 0x4
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#define ONFI_READ_PARAM_PAGE_BUFFER_SIZE 0x200
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#define ONFI_PARAM_PAGE_SIZE 0x100
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#define NAND_8BIT_DEVICE 0x01
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#define NAND_16BIT_DEVICE 0x02
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#define NAND_CW_SIZE_4_BIT_ECC 528
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#define NAND_CW_SIZE_8_BIT_ECC 532
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/* Indicates the data bytes in the user data portion of the code word. */
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#define USER_DATA_BYTES_PER_CW 512
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/* Indicates the number of bytes covered by BCH ECC logic when
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* a codeword is written to a NAND flash device.
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* This is also the number of bytes that are part of the image in CW.
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* 516 bytes = (512 bytes of user data and 4 bytes of spare data)
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*/
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#define DATA_BYTES_IN_IMG_PER_CW 516
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#define NAND_CW_DIV_RIGHT_SHIFT 9
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/* Number of max cw's the driver allows to flash. */
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#define QPIC_NAND_MAX_CWS_IN_PAGE 10
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/* Reset Values for Status registers */
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#define NAND_FLASH_STATUS_RESET 0x00000020
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#define NAND_READ_STATUS_RESET 0x000000C0
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/* NANDc BAM pipe numbers */
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#define DATA_CONSUMER_PIPE 0
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#define DATA_PRODUCER_PIPE 1
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#define CMD_PIPE 2
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/* NANDc BAM pipe groups */
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#define DATA_PRODUCER_PIPE_GRP 0
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#define DATA_CONSUMER_PIPE_GRP 0
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#define CMD_PIPE_GRP 1
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/* NANDc EE */
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#define QPIC_NAND_EE 0
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/* NANDc max desc length. */
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#define QPIC_NAND_MAX_DESC_LEN 0x7FFF
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/* Register: NAND_CTRL */
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#define BAM_MODE_EN 0x1
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/* Register: NAND_DEBUG */
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#define BAM_MODE_BIT_RESET (1 << 31)
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/* CMD Valid */
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#define NAND_CMD_VALID_BASE 0x1D
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#define NAND_ID_MAN(id) ((id) & 0xFF)
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#define NAND_ID_DEV(id) (((id) >> 8) & 0xFF)
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#define NAND_ID_CFG(id) (((id) >> 24) & 0xFF)
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#define NAND_CFG_PAGE_SIZE(id) (((id) >> 0) & 0x3)
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#define NAND_CFG_SPARE_SIZE(id) (((id) >> 2) & 0x3)
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#define NAND_CFG_BLOCK_SIZE(id) (((id) >> 4) & 0x3)
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#define CHUNK_SIZE 512
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#define MB_TO_BYTES(mb) (((uint64_t)(mb)) << 20)
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#define KB_TO_BYTES(kb) ((kb) << 10)
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#define MTD_NAND_CHIP(mtd) ((struct nand_chip *)((mtd)->priv))
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#define MTD_QPIC_NAND_DEV(mtd) (MTD_NAND_CHIP(mtd)->priv)
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#define QPIC_BAM_DATA_FIFO_SIZE 64
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#define QPIC_BAM_CMD_FIFO_SIZE 64
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enum qpic_verion{
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QCOM_QPIC_V1_4_20,
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QCOM_QPIC_V1_5_20,
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};
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/* result type */
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typedef enum {
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NANDC_RESULT_SUCCESS = 0,
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NANDC_RESULT_FAILURE = 1,
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NANDC_RESULT_TIMEOUT = 2,
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NANDC_RESULT_PARAM_INVALID = 3,
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NANDC_RESULT_DEV_NOT_SUPPORTED = 4,
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NANDC_RESULT_BAD_PAGE = 5,
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NANDC_RESULT_BAD_BLOCK = 6,
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} nand_result_t;
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enum nand_bad_block_value
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{
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NAND_BAD_BLK_VALUE_NOT_READ,
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NAND_BAD_BLK_VALUE_IS_BAD,
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NAND_BAD_BLK_VALUE_IS_GOOD,
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};
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enum nand_cfg_value
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{
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NAND_CFG_RAW,
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NAND_CFG,
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};
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struct onfi_param_page
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{
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uint32_t signature;
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uint16_t rev;
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uint16_t feature_supported;
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uint16_t opt_cmd_supported;
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uint8_t reserved_1[22];
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uint8_t mib[12];
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uint8_t device_model[20];
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uint8_t manufacturer_id;
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uint16_t date_code;
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uint8_t reserved_2[13];
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uint32_t data_per_pg;
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uint16_t spare_per_pg;
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uint32_t data_per_partial_pg;
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uint16_t spare_per_partial_pg;
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uint32_t pgs_per_blk;
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uint32_t blks_per_LUN;
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uint8_t num_LUN;
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uint8_t num_addr_cycles;
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uint8_t num_bits_per_cell;
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uint16_t bad_blks_max_per_LUN;
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uint16_t blk_endurance;
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uint8_t guaranteed_vld_blks_at_start;
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uint16_t blk_endurance_for_garunteed_vld_blks;
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uint8_t num_prg_per_pg;
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uint8_t partial_prog_attr;
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uint8_t num_bits_ecc_correctability;
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uint8_t num_interleaved_addr_bits;
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uint8_t interleaved_op_attr;
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uint8_t reserved_3[13];
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uint8_t io_pin_capcacitance;
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uint16_t timing_mode_support;
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uint16_t prog_cache_timing_mode_support;
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uint16_t max_pg_prog_time_us;
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uint16_t max_blk_erase_time_us;
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uint16_t max_pr_rd_time_us;
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uint16_t min_chg_col_setup_time_us;
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uint8_t reserved_4[23];
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uint16_t vendor_rev;
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uint8_t vendor_specific[88];
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uint16_t interity_crc;
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}__packed;
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struct cfg_params
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{
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uint32_t addr0;
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uint32_t addr1;
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uint32_t cfg0;
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uint32_t cfg1;
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uint32_t cmd;
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uint32_t ecc_cfg;
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uint32_t addr_loc_0;
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uint32_t exec;
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};
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struct onfi_probe_params
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{
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uint32_t vld;
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uint32_t dev_cmd1;
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struct cfg_params cfg;
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};
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/* This stucture is used to create a static list of devices we support.
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* This include a subset of values defined in the flash_info struct as
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* other values can be derived.
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*/
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struct flash_id
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{
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unsigned flash_id;
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unsigned mask;
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unsigned density;
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unsigned widebus;
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unsigned pagesize;
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unsigned blksize;
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unsigned oobsize;
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unsigned ecc_8_bits;
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};
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/* Structure to hold the pipe numbers */
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struct qpic_nand_bam_pipes
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{
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unsigned read_pipe;
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unsigned write_pipe;
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unsigned cmd_pipe;
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uint8_t read_pipe_grp;
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uint8_t write_pipe_grp;
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uint8_t cmd_pipe_grp;
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};
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/* Structure to define the initial nand config */
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struct qpic_nand_init_config
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{
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uint32_t nand_base;
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uint32_t bam_base;
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uint32_t ee;
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uint32_t max_desc_len;
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struct qpic_nand_bam_pipes pipes;
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};
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enum nand_ecc_width
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{
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NAND_WITH_4_BIT_ECC,
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NAND_WITH_8_BIT_ECC,
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};
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struct qpic_nand_dev {
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unsigned id;
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unsigned type;
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unsigned vendor;
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unsigned device;
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unsigned page_size;
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unsigned block_size;
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unsigned spare_size;
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unsigned num_blocks;
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enum nand_ecc_width ecc_width;
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unsigned num_pages_per_blk;
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unsigned num_pages_per_blk_mask;
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unsigned widebus;
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unsigned density;
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unsigned cw_size;
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unsigned cws_per_page;
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unsigned bad_blk_loc;
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|
unsigned dev_cfg;
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uint32_t cfg0;
|
|
uint32_t cfg1;
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uint32_t cfg0_raw;
|
|
uint32_t cfg1_raw;
|
|
uint32_t ecc_bch_cfg;
|
|
unsigned oob_per_page;
|
|
unsigned char *buffers;
|
|
unsigned char *pad_dat;
|
|
unsigned char *pad_oob;
|
|
unsigned char *zero_page;
|
|
unsigned char *zero_oob;
|
|
};
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#endif
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