Chin Liang See 89a54abf1b ddr: altera: Configuring SDRAM extra cycles timing parameters ... To enable configuration of sdr.ctrlcfg.extratime1 register which enable extra clocks for read to write command timing. This is critical to ensure successful LPDDR2 interface Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>		2016-10-27 08:03:07 +02:00
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altera	ddr: altera: Configuring SDRAM extra cycles timing parameters	2016-10-27 08:03:07 +02:00
fsl	Merge git://git.denx.de/u-boot-fsl-qoriq	2016-09-26 17:10:56 -04:00
marvell	Various, accumulated typos collected from around the tree.	2016-10-06 20:57:40 -04:00
microchip	drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.	2016-02-01 22:14:01 +01:00