mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
This changes add 4-Bit eMMC flash support Change-Id: Iad789ba44aaa0e11da5f8c16dd0a07d2e80de682 Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
160 lines
5.2 KiB
C
160 lines
5.2 KiB
C
/*
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* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
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*
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DEVSOC_CDP_H_
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#define _DEVSOC_CDP_H_
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#include <configs/devsoc.h>
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#include <asm/u-boot.h>
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#include <asm/arch-qca-common/qca_common.h>
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#include "phy.h"
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extern const char *rsvd_node;
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extern const char *del_node[];
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extern const add_node_t add_fdt_node[];
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#define KERNEL_AUTH_CMD 0x13
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#define SCM_CMD_SEC_AUTH 0x15
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#define BLSP1_UART0_BASE 0x078AF000
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#define UART_PORT_ID(reg) ((reg - BLSP1_UART0_BASE) / 0x1000)
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#define MSM_SDC1_BASE 0x7800000
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#define MSM_SDC1_SDHCI_BASE 0x7804000
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/*
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* weak function
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*/
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__weak void aquantia_phy_reset_init_done(void) {}
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__weak void aquantia_phy_reset_init(void) {}
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__weak void qgic_init(void) {}
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__weak void handle_noc_err(void) {}
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__weak void board_pcie_clock_init(int id) {}
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__weak void ubi_power_collapse(void) {}
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/*
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* SMEM
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*/
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#ifdef CONFIG_SMEM_VERSION_C
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#define RAM_PART_NAME_LENGTH 16
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/**
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* Number of RAM partition entries which are usable by APPS.
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*/
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#define RAM_NUM_PART_ENTRIES 32
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struct ram_partition_entry
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{
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char name[RAM_PART_NAME_LENGTH]; /**< Partition name, unused for now */
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u64 start_address; /**< Partition start address in RAM */
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u64 length; /**< Partition length in RAM in Bytes */
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u32 partition_attribute; /**< Partition attribute */
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u32 partition_category; /**< Partition category */
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u32 partition_domain; /**< Partition domain */
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u32 partition_type; /**< Partition type */
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u32 num_partitions; /**< Number of partitions on device */
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u32 hw_info; /**< hw information such as type and frequency */
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u8 highest_bank_bit; /**< Highest bit corresponding to a bank */
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u8 reserve0; /**< Reserved for future use */
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u8 reserve1; /**< Reserved for future use */
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u8 reserve2; /**< Reserved for future use */
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u32 reserved5; /**< Reserved for future use */
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u64 available_length; /**< Available Partition length in RAM in Bytes */
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};
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struct usable_ram_partition_table
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{
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u32 magic1; /**< Magic number to identify valid RAM partition table */
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u32 magic2; /**< Magic number to identify valid RAM partition table */
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u32 version; /**< Version number to track structure definition changes
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and maintain backward compatibilities */
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u32 reserved1; /**< Reserved for future use */
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u32 num_partitions; /**< Number of RAM partition table entries */
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u32 reserved2; /** < Added for 8 bytes alignment of header */
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/** RAM partition table entries */
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struct ram_partition_entry ram_part_entry[RAM_NUM_PART_ENTRIES];
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};
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#endif
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struct smem_ram_ptn {
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char name[16];
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unsigned long long start;
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unsigned long long size;
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/* RAM Partition attribute: READ_ONLY, READWRITE etc. */
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unsigned attr;
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/* RAM Partition category: EBI0, EBI1, IRAM, IMEM */
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unsigned category;
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/* RAM Partition domain: APPS, MODEM, APPS & MODEM (SHARED) etc. */
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unsigned domain;
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/* RAM Partition type: system, bootloader, appsboot, apps etc. */
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unsigned type;
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/* reserved for future expansion without changing version number */
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unsigned reserved2, reserved3, reserved4, reserved5;
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} __attribute__ ((__packed__));
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struct smem_ram_ptable {
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#define _SMEM_RAM_PTABLE_MAGIC_1 0x9DA5E0A8
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#define _SMEM_RAM_PTABLE_MAGIC_2 0xAF9EC4E2
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unsigned magic[2];
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unsigned version;
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unsigned reserved1;
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unsigned len;
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unsigned buf;
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struct smem_ram_ptn parts[32];
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} __attribute__ ((__packed__));
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typedef enum {
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SMEM_SPINLOCK_ARRAY = 7,
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SMEM_AARM_PARTITION_TABLE = 9,
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SMEM_HW_SW_BUILD_ID = 137,
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SMEM_USABLE_RAM_PARTITION_TABLE = 402,
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SMEM_POWER_ON_STATUS_INFO = 403,
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SMEM_MACHID_INFO_LOCATION = 425,
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SMEM_IMAGE_VERSION_TABLE = 469,
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SMEM_BOOT_FLASH_TYPE = 498,
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SMEM_BOOT_FLASH_INDEX = 499,
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SMEM_BOOT_FLASH_CHIP_SELECT = 500,
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SMEM_BOOT_FLASH_BLOCK_SIZE = 501,
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SMEM_BOOT_FLASH_DENSITY = 502,
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SMEM_BOOT_DUALPARTINFO = 503,
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SMEM_PARTITION_TABLE_OFFSET = 504,
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SMEM_SPI_FLASH_ADDR_LEN = 505,
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SMEM_RUNTIME_FAILSAFE_INFO = 507,
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SMEM_FIRST_VALID_TYPE = SMEM_SPINLOCK_ARRAY,
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SMEM_LAST_VALID_TYPE = SMEM_RUNTIME_FAILSAFE_INFO,
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SMEM_MAX_SIZE = SMEM_RUNTIME_FAILSAFE_INFO + 1,
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} smem_mem_type_t;
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/*
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* function declaration
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*/
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int smem_ram_ptable_init(struct smem_ram_ptable *smem_ram_ptable);
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void reset_crashdump(void);
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void reset_board(void);
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int ipq_get_tz_version(char *version_name, int buf_size);
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void ipq_fdt_fixup_socinfo(void *blob);
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int smem_ram_ptable_init(struct smem_ram_ptable *smem_ram_ptable);
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int smem_ram_ptable_init_v2(
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struct usable_ram_partition_table *usable_ram_partition_table);
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void qpic_set_clk_rate(unsigned int clk_rate, int blk_type,
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int req_clk_src_type);
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#endif /* _DEVSOC_CDP_H_ */
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