mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
270d1e7245
This changes add 4-Bit eMMC flash support Change-Id: Iad789ba44aaa0e11da5f8c16dd0a07d2e80de682 Signed-off-by: Vandhiadevan Karunamoorthy <quic_vkarunam@quicinc.com>
108 lines
3.3 KiB
C
108 lines
3.3 KiB
C
/*
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* Copyright (c) 2015-2016, 2018, 2020 The Linux Foundation. All rights reserved.
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*
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DEVSOC_CLK_H
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#define _DEVSOC_CLK_H
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#include <asm/arch-qca-common/uart.h>
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/*
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* UART registers
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*/
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#define GCC_BLSP1_UART1_BCR 0x1802028
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#define GCC_BLSP1_UART2_BCR 0x1803028
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#define GCC_BLSP1_UART3_BCR 0x1804028
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#define GCC_BLSP1_UART_BCR(id) ((id < 1) ? \
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(GCC_BLSP1_UART1_BCR):\
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(GCC_BLSP1_UART1_BCR + (0x1000 * id)))
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#define GCC_BLSP1_UART_APPS_CMD_RCGR(id) (GCC_BLSP1_UART_BCR(id) + 0x04)
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#define GCC_BLSP1_UART_APPS_CFG_RCGR(id) (GCC_BLSP1_UART_BCR(id) + 0x08)
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#define GCC_BLSP1_UART_APPS_M(id) (GCC_BLSP1_UART_BCR(id) + 0x0c)
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#define GCC_BLSP1_UART_APPS_N(id) (GCC_BLSP1_UART_BCR(id) + 0x10)
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#define GCC_BLSP1_UART_APPS_D(id) (GCC_BLSP1_UART_BCR(id) + 0x14)
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#define GCC_BLSP1_UART_APPS_CBCR(id) (GCC_BLSP1_UART_BCR(id) + 0x18)
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#define GCC_UART_CFG_RCGR_MODE_MASK 0x3000
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#define GCC_UART_CFG_RCGR_SRCSEL_MASK 0x0700
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#define GCC_UART_CFG_RCGR_SRCDIV_MASK 0x001F
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#define GCC_UART_CFG_RCGR_MODE_SHIFT 12
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#define GCC_UART_CFG_RCGR_SRCSEL_SHIFT 8
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#define GCC_UART_CFG_RCGR_SRCDIV_SHIFT 0
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#define UART_RCGR_SRC_SEL 0x1
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#define UART_RCGR_SRC_DIV 0x0
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#define UART_RCGR_MODE 0x2
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#define UART_CMD_RCGR_UPDATE 0x1
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#define UART_CMD_RCGR_ROOT_EN 0x2
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#define UART_CBCR_CLK_ENABLE 0x1
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#define NOT_2D(two_d) (~two_d)
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#define NOT_N_MINUS_M(n,m) (~(n - m))
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#define CLOCK_UPDATE_TIMEOUT_US 1000
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#define CMD_UPDATE 0x1
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#define ROOT_EN 0x2
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#define CLK_ENABLE 0x1
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/*
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* Qpic SPI Nand clock
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*/
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#define GCC_QPIC_IO_MACRO_CMD_RCGR 0x1832004
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#define GCC_QPIC_IO_MACRO_CFG_RCGR 0x1832008
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#define GCC_QPIC_IO_MACRO_CBCR 0x183200C
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#define GCC_QPIC_AHB_CBCR_ADDR 0x1832010
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#define GCC_QPIC_CBCR_ADDR 0x1832014
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#define GCC_QPIC_SREGR 0x1832018
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#define GCC_QPIC_SLEEP_CBCR 0x183201C
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#define IO_MACRO_CLK_320_MHZ 320000000
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#define IO_MACRO_CLK_266_MHZ 266000000
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#define IO_MACRO_CLK_228_MHZ 228000000
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#define IO_MACRO_CLK_200_MHZ 200000000
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#define IO_MACRO_CLK_100_MHZ 100000000
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#define IO_MACRO_CLK_24MHZ 24000000
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#define QPIC_IO_MACRO_CLK 0
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#define QPIC_CORE_CLK 1
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#define XO_CLK_SRC 2
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#define GPLL0_CLK_SRC 3
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#define FB_CLK_BIT (1 << 4)
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#define UPDATE_EN 0x1
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/*
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* GCC-SDCC Registers
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*/
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#define GCC_SDCC1_BCR 0x01833000
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#define GCC_SDCC1_APPS_CMD_RCGR 0x01833004
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#define GCC_SDCC1_APPS_CFG_RCGR 0x01833008
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#define GCC_SDCC1_APPS_M 0x0183300C
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#define GCC_SDCC1_APPS_N 0x01833010
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#define GCC_SDCC1_APPS_D 0x01833014
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#define GCC_SDCC1_APPS_CBCR 0x01833034
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#define GCC_SDCC1_AHB_CBCR 0x0183301C
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#ifdef CONFIG_QCA_MMC
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void emmc_clock_init(void);
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void emmc_clock_reset(void);
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#endif
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int uart_clock_config(struct ipq_serial_platdata *plat);
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#endif /*IPQ9574_CLK_H*/
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