mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
18d2b93ab3
This patch adds initial support for qca8084 PHY which is based on qca8081 PHY. qca8084 PHY has support for 4x2.5G. Change-Id: Ic767c19fad050e5ee9a97ad7fa50c1b6b27893dd Signed-off-by: Selvam Sathappan Periakaruppan <quic_speriaka@quicinc.com>
183 lines
7.2 KiB
C
183 lines
7.2 KiB
C
/*
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* Copyright (c) 2022, The Linux Foundation. All rights reserved.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _QCA8084_CLK_H_
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#define _QCA8084_CLK_H_
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#define QCA8084_SWITCH_CORE_CLK "qca8084_gcc_switch_core_clk"
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#define QCA8084_APB_BRIDGE_CLK "qca8084_gcc_apb_bridge_clk"
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#define QCA8084_MAC0_TX_CLK "qca8084_gcc_mac0_tx_clk"
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#define QCA8084_MAC0_TX_UNIPHY1_CLK "qca8084_gcc_mac0_tx_srds1_clk"
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#define QCA8084_MAC0_RX_CLK "qca8084_gcc_mac0_rx_clk"
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#define QCA8084_MAC0_RX_UNIPHY1_CLK "qca8084_gcc_mac0_rx_srds1_clk"
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#define QCA8084_MAC1_TX_CLK "qca8084_gcc_mac1_tx_clk"
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#define QCA8084_MAC1_GEPHY0_TX_CLK "qca8084_gcc_mac1_gephy0_tx_clk"
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#define QCA8084_MAC1_UNIPHY1_CH0_RX_CLK "qca8084_gcc_mac1_srds1_ch0_rx_clk"
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#define QCA8084_MAC1_UNIPHY1_CH0_XGMII_RX_CLK "qca8084_gcc_mac1_srds1_ch0_xgmii_rx_clk"
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#define QCA8084_MAC1_RX_CLK "qca8084_gcc_mac1_rx_clk"
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#define QCA8084_MAC1_GEPHY0_RX_CLK "qca8084_gcc_mac1_gephy0_rx_clk"
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#define QCA8084_MAC1_UNIPHY1_CH0_TX_CLK "qca8084_gcc_mac1_srds1_ch0_tx_clk"
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#define QCA8084_MAC1_UNIPHY1_CH0_XGMII_TX_CLK "qca8084_gcc_mac1_srds1_ch0_xgmii_tx_clk"
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#define QCA8084_MAC2_TX_CLK "qca8084_gcc_mac2_tx_clk"
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#define QCA8084_MAC2_GEPHY1_TX_CLK "qca8084_gcc_mac2_gephy1_tx_clk"
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#define QCA8084_MAC2_UNIPHY1_CH1_RX_CLK "qca8084_gcc_mac2_srds1_ch1_rx_clk"
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#define QCA8084_MAC2_UNIPHY1_CH1_XGMII_RX_CLK "qca8084_gcc_mac2_srds1_ch1_xgmii_rx_clk"
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#define QCA8084_MAC2_RX_CLK "qca8084_gcc_mac2_rx_clk"
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#define QCA8084_MAC2_GEPHY1_RX_CLK "qca8084_gcc_mac2_gephy1_rx_clk"
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#define QCA8084_MAC2_UNIPHY1_CH1_TX_CLK "qca8084_gcc_mac2_srds1_ch1_tx_clk"
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#define QCA8084_MAC2_UNIPHY1_CH1_XGMII_TX_CLK "qca8084_gcc_mac2_srds1_ch1_xgmii_tx_clk"
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#define QCA8084_MAC3_TX_CLK "qca8084_gcc_mac3_tx_clk"
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#define QCA8084_MAC3_GEPHY2_TX_CLK "qca8084_gcc_mac3_gephy2_tx_clk"
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#define QCA8084_MAC3_UNIPHY1_CH2_RX_CLK "qca8084_gcc_mac3_srds1_ch2_rx_clk"
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#define QCA8084_MAC3_UNIPHY1_CH2_XGMII_RX_CLK "qca8084_gcc_mac3_srds1_ch2_xgmii_rx_clk"
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#define QCA8084_MAC3_RX_CLK "qca8084_gcc_mac3_rx_clk"
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#define QCA8084_MAC3_GEPHY2_RX_CLK "qca8084_gcc_mac3_gephy2_rx_clk"
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#define QCA8084_MAC3_UNIPHY1_CH2_TX_CLK "qca8084_gcc_mac3_srds1_ch2_tx_clk"
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#define QCA8084_MAC3_UNIPHY1_CH2_XGMII_TX_CLK "qca8084_gcc_mac3_srds1_ch2_xgmii_tx_clk"
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#define QCA8084_MAC4_TX_CLK "qca8084_gcc_mac4_tx_clk"
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#define QCA8084_MAC4_GEPHY3_TX_CLK "qca8084_gcc_mac4_gephy3_tx_clk"
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#define QCA8084_MAC4_UNIPHY1_CH3_RX_CLK "qca8084_gcc_mac4_srds1_ch3_rx_clk"
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#define QCA8084_MAC4_UNIPHY1_CH3_XGMII_RX_CLK "qca8084_gcc_mac4_srds1_ch3_xgmii_rx_clk"
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#define QCA8084_MAC4_RX_CLK "qca8084_gcc_mac4_rx_clk"
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#define QCA8084_MAC4_GEPHY3_RX_CLK "qca8084_gcc_mac4_gephy3_rx_clk"
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#define QCA8084_MAC4_UNIPHY1_CH3_TX_CLK "qca8084_gcc_mac4_srds1_ch3_tx_clk"
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#define QCA8084_MAC4_UNIPHY1_CH3_XGMII_TX_CLK "qca8084_gcc_mac4_srds1_ch3_xgmii_tx_clk"
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#define QCA8084_MAC5_TX_CLK "qca8084_gcc_mac5_tx_clk"
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#define QCA8084_MAC5_TX_UNIPHY0_CLK "qca8084_gcc_mac5_tx_srds0_clk"
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#define QCA8084_MAC5_TX_SRDS0_CLK_SRC "qca8084_gcc_mac5_tx_srds0_clk_src"
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#define QCA8084_MAC5_RX_CLK "qca8084_gcc_mac5_rx_clk"
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#define QCA8084_MAC5_RX_UNIPHY0_CLK "qca8084_gcc_mac5_rx_srds0_clk"
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#define QCA8084_MAC5_RX_SRDS0_CLK_SRC "qca8084_gcc_mac5_rx_srds0_clk_src"
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#define QCA8084_SEC_CTRL_CLK "qca8084_gcc_sec_ctrl_clk"
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#define QCA8084_SEC_CTRL_SENSE_CLK "qca8084_gcc_sec_ctrl_sense_clk"
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#define QCA8084_SRDS0_SYS_CLK "qca8084_gcc_srds0_sys_clk"
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#define QCA8084_SRDS1_SYS_CLK "qca8084_gcc_srds1_sys_clk"
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#define QCA8084_GEPHY0_SYS_CLK "qca8084_gcc_gephy0_sys_clk"
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#define QCA8084_GEPHY1_SYS_CLK "qca8084_gcc_gephy1_sys_clk"
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#define QCA8084_GEPHY2_SYS_CLK "qca8084_gcc_gephy2_sys_clk"
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#define QCA8084_GEPHY3_SYS_CLK "qca8084_gcc_gephy3_sys_clk"
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#define QCA8084_AHB_CLK "qca8084_gcc_ahb_clk"
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#define QCA8084_SEC_CTRL_AHB_CLK "qca8084_gcc_sec_ctrl_ahb_clk"
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#define QCA8084_TLMM_CLK "qca8084_gcc_tlmm_clk"
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#define QCA8084_TLMM_AHB_CLK "qca8084_gcc_tlmm_ahb_clk"
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#define QCA8084_CNOC_AHB_CLK "qca8084_gcc_cnoc_ahb_clk"
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#define QCA8084_MDIO_AHB_CLK "qca8084_gcc_mdio_ahb_clk"
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#define QCA8084_MDIO_MASTER_AHB_CLK "qca8084_gcc_mdio_master_ahb_clk"
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#define QCA8084_GLOBAL_RST "qca8084_gcc_global_rst"
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#define QCA8084_UNIPHY_XPCS_RST "qca8084_uniphy_xpcs_rst"
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#define QCA8084_GEPHY_DSP_HW_RST "qca8084_gephy_dsp_hw_rst"
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#define QCA8084_GEPHY_P3_MDC_SW_RST "qca8084_gephy_p3_mdc_sw_rst"
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#define QCA8084_GEPHY_P2_MDC_SW_RST "qca8084_gephy_p2_mdc_sw_rst"
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#define QCA8084_GEPHY_P1_MDC_SW_RST "qca8084_gephy_p1_mdc_sw_rst"
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#define QCA8084_GEPHY_P0_MDC_SW_RST "qca8084_gephy_p0_mdc_sw_rst"
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typedef enum {
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QCA8084_P_XO,
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QCA8084_P_UNIPHY0_RX,
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QCA8084_P_UNIPHY0_TX,
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QCA8084_P_UNIPHY1_RX,
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QCA8084_P_UNIPHY1_TX,
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QCA8084_P_UNIPHY1_RX312P5M,
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QCA8084_P_UNIPHY1_TX312P5M,
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QCA8084_P_MAX,
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} qca8084_clk_parent_t;
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struct qca8084_clk_data {
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unsigned long rate;
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unsigned int rcg_val;
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unsigned int cdiv_val;
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unsigned int cbc_val;
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};
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struct qca8084_parent_data {
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unsigned long prate; /* RCG input clock rate */
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qca8084_clk_parent_t parent; /* RCG parent clock id */
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int cfg; /* RCG clock src value */
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};
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struct clk_lookup {
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unsigned int rcg;
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unsigned int cdiv;
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unsigned int cbc;
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unsigned int rst_bit;
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const char *clk_name;
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const unsigned long *support_rate;
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unsigned int num_rate;
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const struct qca8084_parent_data *pdata;
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unsigned int num_parent;
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};
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#define CLK_LOOKUP(_rcg, _cdiv, _cbc, _rst_bit, _clk_name, \
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_rate, _num_rate, _pdata, _num_parent) \
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{ \
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.rcg = _rcg, \
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.cdiv = _cdiv, \
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.cbc = _cbc, \
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.rst_bit = _rst_bit, \
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.clk_name = _clk_name, \
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.support_rate = _rate, \
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.num_rate = _num_rate, \
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.pdata = _pdata, \
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.num_parent = _num_parent, \
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}
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#define QCA8084_CLK_TYPE_EPHY BIT(0)
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#define QCA8084_CLK_TYPE_UNIPHY BIT(1)
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#define QCA8084_CLK_TYPE_MAC BIT(2)
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#define UQXGMII_SPEED_2500M_CLK 312500000
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#define UQXGMII_SPEED_1000M_CLK 125000000
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#define UQXGMII_SPEED_100M_CLK 25000000
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#define UQXGMII_SPEED_10M_CLK 2500000
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#define UQXGMII_XPCS_SPEED_2500M_CLK 78125000
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#define QCA8084_AHB_CLK_RATE_104P17M 104160000
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#define QCA8084_SYS_CLK_RATE_25M 25000000
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#define QCA8084_XO_CLK_RATE_50M 50000000
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#define QCA8084_CLK_BASE_REG 0x0c800000
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#define QCA8084_CLK_MUX_SEL 0x300
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#define QCA8084_UNIPHY0_MUX_SEL_MASK BITS_MASK(0, 2)
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#define QCA8084_UNIPHY0_SEL_MAC5 0x3
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#define QCA8084_UNIPHY0_SEL_MAC4 0
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#define RCGR_CMD_ROOT_OFF BIT(31)
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#define RCGR_CMD_UPDATE BIT(0)
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#define RCGR_SRC_SEL BITS_MASK(8, 3)
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#define RCGR_SRC_SEL_SHIFT 8
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#define RCGR_HDIV BITS_MASK(0, 5)
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#define RCGR_HDIV_SHIFT 0
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#define RCGR_DIV_BYPASS 0
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#define RCGR_DIV_MAX 0x1f
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#define CDIVR_DIVIDER_10 9 /* CDIVR divided by N + 1 */
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#define CDIVR_DIVIDER BITS_MASK(0, 4)
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#define CDIVR_DIVIDER_SHIFT 0
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#define CBCR_CLK_OFF BIT(31)
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#define CBCR_CLK_RESET BIT(2)
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#define CBCR_CLK_ENABLE BIT(0)
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#endif /* _QCA8084_CLK_H_ */
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