mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
18d2b93ab3
This patch adds initial support for qca8084 PHY which is based on qca8081 PHY. qca8084 PHY has support for 4x2.5G. Change-Id: Ic767c19fad050e5ee9a97ad7fa50c1b6b27893dd Signed-off-by: Selvam Sathappan Periakaruppan <quic_speriaka@quicinc.com>
80 lines
2.6 KiB
C
80 lines
2.6 KiB
C
/*
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* Copyright (c) 2022, The Linux Foundation. All rights reserved.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _QCA8084_PHY_H_
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#define _QCA8084_PHY_H_
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/*MII register*/
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#define QCA8084_PHY_FIFO_CONTROL 0x19
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/*MII register field*/
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#define QCA8084_PHY_FIFO_RESET 0x3
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/*MMD1 register*/
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#define QCA8084_PHY_MMD1_NUM 0x1
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/*MMD3 register*/
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#define QCA8084_PHY_MMD3_NUM 0x3
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#define QCA8084_PHY_MMD3_ADDR_8023AZ_EEE_2500M_CAPABILITY 0x15
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#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL3 0x8074
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#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL4 0x8075
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#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL5 0x8076
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#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL6 0x8077
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#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL7 0x8078
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#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL9 0x807a
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#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL13 0x807e
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#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL14 0x807f
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/*MMD3 register field*/
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#define QCA8084_PHY_EEE_CAPABILITY_2500M 0x1
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#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL3_VAL 0xc040
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#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL4_VAL 0xa060
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#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL5_VAL 0xc040
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#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL6_VAL 0xa060
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#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL7_VAL 0xc050
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#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL9_VAL 0xc060
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#define QCA8084_PHY_MMD3_CDT_THRESH_CTRL13_VAL 0xb060
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#define QCA8084_PHY_MMD3_NEAR_ECHO_THRESH_VAL 0x1eb0
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/*MMD7 register*/
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#define QCA8084_PHY_MMD7_NUM 0x7
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#define QCA8084_PHY_MMD7_ADDR_8023AZ_EEE_2500M_CTRL 0x3e
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#define QCA8084_PHY_MMD7_ADDR_8023AZ_EEE_2500M_PARTNER 0x3f
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#define QCA8084_PHY_MMD7_IPG_10_11_ENABLE 0x901d
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/*MMD7 register field*/
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#define QCA8084_PHY_8023AZ_EEE_2500BT 0x1
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#define QCA8084_PHY_MMD7_IPG_10_EN 0
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#define QCA8084_PHY_MMD7_IPG_11_EN 0x1
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/*DEBUG port analog register*/
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#define QCA8084_PHY_DEBUG_ANA_INTERFACE_CLK_SEL 0x8b80
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#define QCA8084_DEBUG_PORT_ADDRESS 29
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#define QCA8084_DEBUG_PORT_DATA 30
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#define QCA8084_PHY_CONTROL 0
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#define QCA8084_CTRL_SOFTWARE_RESET 0x8000
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#define PHY_INVALID_DATA 0xffff
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#define QCA8084_MII_ADDR_C45 (1<<30)
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#define QCA8084_REG_C45_ADDRESS(dev_type, reg_num) (QCA8084_MII_ADDR_C45 | \
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((dev_type & 0x1f) << 16) | (reg_num & 0xffff))
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typedef enum {
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ADC_RISING = 0,
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ADC_FALLING = 0xf0,
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}
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qca8084_adc_edge_t;
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#endif
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