mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
18d2b93ab3
This patch adds initial support for qca8084 PHY which is based on qca8081 PHY. qca8084 PHY has support for 4x2.5G. Change-Id: Ic767c19fad050e5ee9a97ad7fa50c1b6b27893dd Signed-off-by: Selvam Sathappan Periakaruppan <quic_speriaka@quicinc.com>
280 lines
9.1 KiB
C
280 lines
9.1 KiB
C
/*
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* Copyright (c) 2022, The Linux Foundation. All rights reserved.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "ipq_phy.h"
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#include "ipq_qca8081.h"
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#include "ipq_qca8084.h"
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#include "ipq_qca8084_clk.h"
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#include <linux/compat.h>
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#include <malloc.h>
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#ifdef DEBUG
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#define pr_debug(fmt, args...) printf(fmt, ##args);
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#else
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#define pr_debug(fmt, args...)
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#endif
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extern int ipq_mdio_read(int mii_id,
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int regnum, ushort *data);
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extern int ipq_mdio_write(int mii_id,
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int regnum, u16 data);
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extern void qca8084_interface_uqxgmii_mode_set(void);
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extern void qca8084_gcc_clock_init(void);
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extern u8 qca8081_phy_get_link_status(u32 dev_id, u32 phy_id);
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extern u32 qca8081_phy_get_duplex(u32 dev_id, u32 phy_id, fal_port_duplex_t *duplex);
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extern u32 qca8081_phy_get_speed(u32 dev_id, u32 phy_id, fal_port_speed_t *speed);
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extern void qca8084_uniphy_xpcs_autoneg_restart(uint32_t qca8084_port_id);
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extern void qca8084_port_speed_clock_set(uint32_t qca8084_port_id,
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fal_port_speed_t speed);
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extern void qca8084_uniphy_xpcs_speed_set(uint32_t qca8084_port_id,
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fal_port_speed_t speed);
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extern void qca8084_port_clk_en_set(uint32_t qca8084_port_id, uint8_t mask,
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uint8_t enable);
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extern void qca8084_port_clk_reset(uint32_t qca8084_port_id, uint8_t mask);
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extern void qca8084_uniphy_uqxgmii_function_reset(uint32_t qca8084_port_id);
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u16 qca8084_phy_reg_read(u32 phy_addr, u32 reg_id)
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{
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return ipq_mdio_read(phy_addr, reg_id, NULL);
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}
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u16 qca8084_phy_reg_write(u32 phy_addr, u32 reg_id, u16 value)
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{
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return ipq_mdio_write(phy_addr, reg_id, value);
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}
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u16 qca8084_phy_mmd_read(u32 phy_addr, u16 mmd_num, u16 reg_id)
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{
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uint32_t reg_id_c45 = QCA8084_REG_C45_ADDRESS(mmd_num, reg_id);
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return ipq_mdio_read(phy_addr, reg_id_c45, NULL);
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}
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u16 qca8084_phy_mmd_write(u32 phy_addr, u16 mmd_num, u16 reg_id, u16 value)
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{
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uint32_t reg_id_c45 = QCA8084_REG_C45_ADDRESS(mmd_num, reg_id);
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return ipq_mdio_write(phy_addr, reg_id_c45, value);
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}
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void qca8084_phy_modify_mii(uint32_t phy_addr, uint32_t mii_reg, uint32_t mask,
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uint32_t value)
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{
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uint16_t phy_data = 0, new_phy_data = 0;
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phy_data = qca8084_phy_reg_read(phy_addr, mii_reg);
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new_phy_data = (phy_data & ~mask) | value;
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qca8084_phy_reg_write(phy_addr, mii_reg, new_phy_data);
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/*check the mii register value*/
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phy_data = qca8084_phy_reg_read(phy_addr, mii_reg);
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pr_debug("phy_addr:0x%x, mii_reg:0x%x, phy_data:0x%x\n",
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phy_addr, mii_reg, phy_data);
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}
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void qca8084_phy_modify_mmd(uint32_t phy_addr, uint32_t mmd_num,
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uint32_t mmd_reg, uint32_t mask, uint32_t value)
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{
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uint16_t phy_data = 0, new_phy_data = 0;
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phy_data = qca8084_phy_mmd_read(phy_addr, mmd_num, mmd_reg);
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new_phy_data = (phy_data & ~mask) | value;
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qca8084_phy_mmd_write(phy_addr, mmd_num, mmd_reg, new_phy_data);
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/* check the mmd register value */
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phy_data = qca8084_phy_mmd_read(phy_addr, mmd_num, mmd_reg);
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pr_debug("phy_addr:0x%x, mmd_reg:0x%x, phy_data:0x%x\n",
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phy_addr, mmd_reg, phy_data);
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}
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void qca8084_phy_ipg_config(uint32_t phy_id, fal_port_speed_t speed)
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{
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uint16_t phy_data = 0;
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phy_data = qca8084_phy_mmd_read(phy_id, QCA8084_PHY_MMD7_NUM,
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QCA8084_PHY_MMD7_IPG_10_11_ENABLE);
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phy_data &= ~QCA8084_PHY_MMD7_IPG_11_EN;
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/*If speed is 1G, enable 11 ipg tuning*/
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pr_debug("if speed is 1G, enable 11 ipg tuning\n");
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if (speed == FAL_SPEED_1000)
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phy_data |= QCA8084_PHY_MMD7_IPG_11_EN;
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qca8084_phy_mmd_write(phy_id, QCA8084_PHY_MMD7_NUM,
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QCA8084_PHY_MMD7_IPG_10_11_ENABLE, phy_data);
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}
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void qca8084_phy_function_reset(uint32_t phy_id)
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{
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uint16_t phy_data = 0;
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phy_data = qca8084_phy_reg_read(phy_id, QCA8084_PHY_FIFO_CONTROL);
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qca8084_phy_reg_write(phy_id, QCA8084_PHY_FIFO_CONTROL,
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phy_data & (~QCA8084_PHY_FIFO_RESET));
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mdelay(50);
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qca8084_phy_reg_write(phy_id, QCA8084_PHY_FIFO_CONTROL,
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phy_data | QCA8084_PHY_FIFO_RESET);
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}
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void qca8084_phy_uqxgmii_speed_fixup(uint32_t phy_addr, uint32_t qca8084_port_id,
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uint32_t status, fal_port_speed_t new_speed)
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{
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uint32_t port_clock_en = 0;
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/*Restart the auto-neg of uniphy*/
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pr_debug("Restart the auto-neg of uniphy\n");
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qca8084_uniphy_xpcs_autoneg_restart(qca8084_port_id);
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/*set gmii+ clock to uniphy1 and ethphy*/
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pr_debug("set gmii,xgmii clock to uniphy and gmii to ethphy\n");
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qca8084_port_speed_clock_set(qca8084_port_id, new_speed);
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/*set xpcs speed*/
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pr_debug("set xpcs speed\n");
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qca8084_uniphy_xpcs_speed_set(qca8084_port_id, new_speed);
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/*GMII/XGMII clock and ETHPHY GMII clock enable/disable*/
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pr_debug("GMII/XGMII clock and ETHPHY GMII clock enable/disable\n");
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if (status == 0)
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port_clock_en = 1;
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qca8084_port_clk_en_set(qca8084_port_id,
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QCA8084_CLK_TYPE_UNIPHY | QCA8084_CLK_TYPE_EPHY,
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port_clock_en);
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pr_debug("UNIPHY GMII/XGMII interface and ETHPHY GMII interface reset and release\n");
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qca8084_port_clk_reset(qca8084_port_id,
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QCA8084_CLK_TYPE_UNIPHY | QCA8084_CLK_TYPE_EPHY);
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pr_debug("ipg_tune and xgmii2gmii reset for uniphy and ETHPHY, function reset\n");
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qca8084_uniphy_uqxgmii_function_reset(qca8084_port_id);
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/*do ethphy function reset: PHY_FIFO_RESET*/
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pr_debug("do ethphy function reset\n");
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qca8084_phy_function_reset(phy_addr);
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/*change IPG from 10 to 11 for 1G speed*/
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qca8084_phy_ipg_config(phy_addr, new_speed);
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}
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void qca8084_phy_interface_mode_set(void)
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{
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pr_debug("Configure QCA8084 as PORT_UQXGMII..\n");
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/*the work mode is PORT_UQXGMII in default*/
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qca8084_interface_uqxgmii_mode_set();
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/*init clock for PORT_UQXGMII*/
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qca8084_gcc_clock_init();
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/*init pinctrl for phy mode to be added later*/
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}
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void qca8084_cdt_thresh_init(u32 phy_id)
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{
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qca8084_phy_mmd_write(phy_id, QCA8084_PHY_MMD3_NUM,
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QCA8084_PHY_MMD3_CDT_THRESH_CTRL3,
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QCA8084_PHY_MMD3_CDT_THRESH_CTRL3_VAL);
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qca8084_phy_mmd_write(phy_id, QCA8084_PHY_MMD3_NUM,
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QCA8084_PHY_MMD3_CDT_THRESH_CTRL4,
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QCA8084_PHY_MMD3_CDT_THRESH_CTRL4_VAL);
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qca8084_phy_mmd_write(phy_id, QCA8084_PHY_MMD3_NUM,
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QCA8084_PHY_MMD3_CDT_THRESH_CTRL5,
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QCA8084_PHY_MMD3_CDT_THRESH_CTRL5_VAL);
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qca8084_phy_mmd_write(phy_id, QCA8084_PHY_MMD3_NUM,
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QCA8084_PHY_MMD3_CDT_THRESH_CTRL6,
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QCA8084_PHY_MMD3_CDT_THRESH_CTRL6_VAL);
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qca8084_phy_mmd_write(phy_id, QCA8084_PHY_MMD3_NUM,
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QCA8084_PHY_MMD3_CDT_THRESH_CTRL7,
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QCA8084_PHY_MMD3_CDT_THRESH_CTRL7_VAL);
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qca8084_phy_mmd_write(phy_id, QCA8084_PHY_MMD3_NUM,
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QCA8084_PHY_MMD3_CDT_THRESH_CTRL9,
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QCA8084_PHY_MMD3_CDT_THRESH_CTRL9_VAL);
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qca8084_phy_mmd_write(phy_id, QCA8084_PHY_MMD3_NUM,
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QCA8084_PHY_MMD3_CDT_THRESH_CTRL13,
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QCA8084_PHY_MMD3_CDT_THRESH_CTRL13_VAL);
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qca8084_phy_mmd_write(phy_id, QCA8084_PHY_MMD3_NUM,
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QCA8084_PHY_MMD3_CDT_THRESH_CTRL14,
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QCA8084_PHY_MMD3_NEAR_ECHO_THRESH_VAL);
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}
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void qca8084_phy_modify_debug(u32 phy_addr, u32 debug_reg,
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u32 mask, u32 value)
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{
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u16 phy_data = 0, new_phy_data = 0;
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qca8084_phy_reg_write(phy_addr, QCA8084_DEBUG_PORT_ADDRESS, debug_reg);
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phy_data = qca8084_phy_reg_read(phy_addr, QCA8084_DEBUG_PORT_DATA);
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if (phy_data == PHY_INVALID_DATA)
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pr_debug("qca8084_phy_reg_read failed\n");
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new_phy_data = (phy_data & ~mask) | value;
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qca8084_phy_reg_write(phy_addr, QCA8084_DEBUG_PORT_ADDRESS, debug_reg);
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qca8084_phy_reg_write(phy_addr, QCA8084_DEBUG_PORT_DATA, new_phy_data);
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/* check debug register value */
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qca8084_phy_reg_write(phy_addr, QCA8084_DEBUG_PORT_ADDRESS, debug_reg);
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phy_data = qca8084_phy_reg_read(phy_addr, QCA8084_DEBUG_PORT_DATA);
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pr_debug("phy_addr:0x%x, debug_reg:0x%x, phy_data:0x%x\n",
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phy_addr, debug_reg, phy_data);
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}
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void qca8084_phy_reset(u32 phy_addr)
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{
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u16 phy_data;
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phy_data = qca8084_phy_reg_read(phy_addr, QCA8084_PHY_CONTROL);
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qca8084_phy_reg_write(phy_addr, QCA8084_PHY_CONTROL,
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phy_data | QCA8084_CTRL_SOFTWARE_RESET);
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}
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void qca8084_phy_adc_edge_set(u32 phy_addr, u32 adc_edge)
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{
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qca8084_phy_modify_debug(phy_addr,
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QCA8084_PHY_DEBUG_ANA_INTERFACE_CLK_SEL, 0xf0, adc_edge);
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qca8084_phy_reset(phy_addr);
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}
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void ipq_qca8084_phy_hw_init(struct phy_ops **ops, u32 phy_addr)
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{
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#ifdef DEBUG
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u16 phy_data;
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#endif
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struct phy_ops *qca8084_ops;
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qca8084_ops = (struct phy_ops *)malloc(sizeof(struct phy_ops));
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if (!qca8084_ops) {
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pr_debug("Error allocating memory for phy ops\n");
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return;
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}
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/* Note that qca8084 PHY is based on qca8081 PHY and so the following
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* ops functions required would be re-used from qca8081 */
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qca8084_ops->phy_get_link_status = qca8081_phy_get_link_status;
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qca8084_ops->phy_get_speed = qca8081_phy_get_speed;
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qca8084_ops->phy_get_duplex = qca8081_phy_get_duplex;
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*ops = qca8084_ops;
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#ifdef DEBUG
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phy_data = qca8084_phy_reg_read(phy_addr, QCA8081_PHY_ID1);
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printf("PHY ID1: 0x%x\n", phy_data);
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phy_data = qca8084_phy_reg_read(phy_addr, QCA8081_PHY_ID2);
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printf("PHY ID2: 0x%x\n", phy_data);
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#endif
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/* adjust CDT threshold */
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qca8084_cdt_thresh_init(phy_addr);
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/* invert ADC clock edge as falling edge to fix link issue */
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qca8084_phy_adc_edge_set(phy_addr, ADC_FALLING);
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}
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