mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
18d2b93ab3
This patch adds initial support for qca8084 PHY which is based on qca8081 PHY. qca8084 PHY has support for 4x2.5G. Change-Id: Ic767c19fad050e5ee9a97ad7fa50c1b6b27893dd Signed-off-by: Selvam Sathappan Periakaruppan <quic_speriaka@quicinc.com>
156 lines
4.2 KiB
C
Executable file
156 lines
4.2 KiB
C
Executable file
/*
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* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _IPQ_EDMA_H
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#define _IPQ_EDMA_H
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#include <common.h>
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#include <net.h>
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#define PHY_MAX 6
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#define IPQ9574_PHY_MAX 6
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#define IPQ6018_PHY_MAX 5
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#define MDIO_CTRL_0_REG 0x00090040
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#define MDIO_CTRL_0_DIV(x) (x << 0)
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#define MDIO_CTRL_0_MODE (1 << 8)
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#define MDIO_CTRL_0_RES(x) (x << 9)
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#define MDIO_CTRL_0_MDC_MODE (1 << 12)
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#define MDIO_CTRL_0_GPHY(x) (x << 13)
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#define MDIO_CTRL_0_RES1(x) (x << 17)
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#define GP_PULL_DOWN 1
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#define GP_OE_EN (1 << 9)
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#define GP_VM_EN (1 << 11)
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#define GP_PU_RES(x) (x << 13)
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#define QCA8075_RST_VAL (GP_PULL_DOWN | GP_OE_EN | \
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GP_VM_EN | GP_PU_RES(2))
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#define QCA8075_PHY_V1_0_5P 0x004DD0B0
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#define QCA8075_PHY_V1_1_5P 0x004DD0B1
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#define QCA8075_PHY_V1_1_2P 0x004DD0B2
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#define QCA8033_PHY 0x004DD074
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#define QCA8033_PHY_ADDR 0x6
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#define QCA8081_PHY 0x004DD100
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#define QCA8081_1_1_PHY 0x004DD101
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#define QCA8084_PHY 0x004DD180
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#define AQUANTIA_PHY_107 0x03a1b4e2
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#define AQUANTIA_PHY_109 0x03a1b502
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#define AQUANTIA_PHY_111 0x03a1b610
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#define AQUANTIA_PHY_111B0 0x03a1b612
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#define AQUANTIA_PHY_112 0x03a1b660
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#define AQUANTIA_PHY_112C 0x03a1b792
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#define AQUANTIA_PHY_113C_A0 0x31c31C10
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#define AQUANTIA_PHY_113C_A1 0x31c31C11
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#define AQUANTIA_PHY_113C_B0 0x31c31C12
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#define AQUANTIA_PHY_113C_B1 0x31c31C13
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#define AQU_PHY_ADDR 0x7
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#define QCA_PHY_ID1 0x2
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#define QCA_PHY_ID2 0x3
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/* Phy preferred medium type */
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typedef enum {
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QCA8075_PHY_MEDIUM_COPPER = 0,
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QCA8075_PHY_MEDIUM_FIBER = 1, /**< Fiber */
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} qca8075_phy_medium_t;
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/* Phy pages */
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typedef enum {
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QCA8075_PHY_SGBX_PAGES = 0, /* sgbx pages */
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QCA8075_PHY_COPPER_PAGES = 1 /* copper pages */
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} qca8075_phy_reg_pages_t;
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typedef enum {
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FAL_HALF_DUPLEX = 0,
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FAL_FULL_DUPLEX,
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FAL_DUPLEX_BUTT = 0xffff
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} fal_port_duplex_t;
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typedef enum {
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FAL_SPEED_10 = 10,
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FAL_SPEED_100 = 100,
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FAL_SPEED_1000 = 1000,
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FAL_SPEED_2500 = 2500,
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FAL_SPEED_5000 = 5000,
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FAL_SPEED_10000 = 10000,
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FAL_SPEED_BUTT = 0xffff,
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} fal_port_speed_t;
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typedef enum {
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FAL_CABLE_STATUS_NORMAL = 0,
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FAL_CABLE_STATUS_SHORT = 1,
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FAL_CABLE_STATUS_OPENED = 2,
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FAL_CABLE_STATUS_INVALID = 3,
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FAL_CABLE_STATUS_BUTT = 0xffff,
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} fal_cable_status_t;
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enum eport_wrapper_cfg {
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EPORT_WRAPPER_PSGMII = 0,
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EPORT_WRAPPER_PSGMII_RGMII5,
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EPORT_WRAPPER_SGMII0_RGMII5,
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EPORT_WRAPPER_SGMII1_RGMII5,
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EPORT_WRAPPER_PSGMII_RMII0,
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EPORT_WRAPPER_PSGMII_RMII1,
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EPORT_WRAPPER_PSGMII_RMII0_RMII1,
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EPORT_WRAPPER_PSGMII_RGMII4,
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EPORT_WRAPPER_SGMII0_RGMII4,
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EPORT_WRAPPER_SGMII1_RGMII4,
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EPORT_WRAPPER_SGMII4_RGMII4,
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EPORT_WRAPPER_QSGMII,
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EPORT_WRAPPER_SGMII_PLUS,
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EPORT_WRAPPER_USXGMII,
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EPORT_WRAPPER_10GBASE_R,
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EPORT_WRAPPER_SGMII_CHANNEL0,
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EPORT_WRAPPER_SGMII_CHANNEL1,
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EPORT_WRAPPER_SGMII_CHANNEL4,
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EPORT_WRAPPER_RGMII,
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EPORT_WRAPPER_PSGMII_FIBER,
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EPORT_WRAPPER_SGMII_FIBER,
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EPORT_WRAPPER_UQXGMII, /* for four channels qca8084 phy mode*/
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EPORT_WRAPPER_UQXGMII_3CHANNELS, /* for three channels qca8084 phy mode */
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EPORT_WRAPPER_MAX = 0xFF
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};
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enum port_wrapper_cfg {
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PORT_WRAPPER_PSGMII = 0,
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PORT_WRAPPER_SGMII0_RGMII4,
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PORT_WRAPPER_USXGMII,
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PORT_WRAPPER_SGMII1_RGMII4,
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PORT_WRAPPER_SGMII4_RGMII4,
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PORT_WRAPPER_QSGMII,
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PORT_WRAPPER_SGMII_PLUS,
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PORT_WRAPPER_10GBASE_R,
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PORT_WRAPPER_SGMII_FIBER,
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};
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enum phy_mode {
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MALIBU_PHY_TYPE = 1,
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QCA8081_PHY_TYPE = 2,
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AQ_PHY_TYPE = 3,
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QCA8033_PHY_TYPE = 4,
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SFP_PHY_TYPE = 5,
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QCA8084_PHY_TYPE = 6,
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UNUSED_PHY_TYPE = 0xFF,
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};
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typedef struct {
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u32 phy_address;
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u32 phy_type;
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}phy_info_t;
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struct phy_ops {
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u8 (*phy_get_link_status) (u32 dev_id, u32 phy_id);
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u32 (*phy_get_duplex) (u32 dev_id, u32 phy_id,
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fal_port_duplex_t * duplex);
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u32 (*phy_get_speed) (u32 dev_id, u32 phy_id,
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fal_port_speed_t * speed);
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};
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#endif /* _IPQ_EDMA_H */
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