mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
18d2b93ab3
This patch adds initial support for qca8084 PHY which is based on qca8081 PHY. qca8084 PHY has support for 4x2.5G. Change-Id: Ic767c19fad050e5ee9a97ad7fa50c1b6b27893dd Signed-off-by: Selvam Sathappan Periakaruppan <quic_speriaka@quicinc.com>
57 lines
1.9 KiB
C
57 lines
1.9 KiB
C
/*
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* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _IPQ_MDIO_H
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#define _IPQ_MDIO_H
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#define IPQ_MDIO_BASE 0x90000
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#define MDIO_CTRL_0_REG 0x40
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#define MDIO_CTRL_1_REG 0x44
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#define MDIO_CTRL_2_REG 0x48
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#define MDIO_CTRL_3_REG 0x4c
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#define MDIO_CTRL_4_REG 0x50
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#define MDIO_CTRL_4_ACCESS_BUSY (1 << 16)
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#define MDIO_CTRL_4_ACCESS_START (1 << 8)
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#define MDIO_CTRL_4_ACCESS_CODE_READ 0
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#define MDIO_CTRL_4_ACCESS_CODE_WRITE 1
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#define MDIO_CTRL_4_ACCESS_CODE_C45_ADDR 0
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#define MDIO_CTRL_4_ACCESS_CODE_C45_WRITE 1
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#define MDIO_CTRL_4_ACCESS_CODE_C45_READ 2
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#define CTRL_0_REG_DEFAULT_VALUE 0x1500F
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#ifdef MDIO_12_5_MHZ
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#define CTRL_0_REG_C45_DEFAULT_VALUE 0x15107
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#else
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#define CTRL_0_REG_C45_DEFAULT_VALUE 0x1510F
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#endif
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#define IPQ_MDIO_RETRY 1000
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#define IPQ_MDIO_DELAY 5
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/* QCA8084 related MDIO Init macros */
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#define UNIPHY_CFG 0xC90F014
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#define EPHY_CFG 0xC90F018
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#define GEPHY0_TX_CBCR 0xC800058
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#define SRDS0_SYS_CBCR 0xC8001A8
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#define SRDS1_SYS_CBCR 0xC8001AC
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#define EPHY0_SYS_CBCR 0xC8001B0
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#define EPHY1_SYS_CBCR 0xC8001B4
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#define EPHY2_SYS_CBCR 0xC8001B8
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#define EPHY3_SYS_CBCR 0xC8001BC
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#define GCC_GEPHY_MISC 0xC800304
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#define PHY_ADDR_LENGTH 5
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#define PHY_ADDR_NUM 4
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#define UNIPHY_ADDR_NUM 3
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#define MII_HIGH_ADDR_PREFIX 0x18
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#define MII_LOW_ADDR_PREFIX 0x10
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DEFINE_MUTEX(switch_mdio_lock);
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#endif /* End _IPQ_MDIO_H */
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