mirror of
https://git.codelinaro.org/clo/qsdk/oss/boot/u-boot-2016.git
synced 2025-12-10 07:44:53 +01:00
18d2b93ab3
This patch adds initial support for qca8084 PHY which is based on qca8081 PHY. qca8084 PHY has support for 4x2.5G. Change-Id: Ic767c19fad050e5ee9a97ad7fa50c1b6b27893dd Signed-off-by: Selvam Sathappan Periakaruppan <quic_speriaka@quicinc.com>
465 lines
10 KiB
C
465 lines
10 KiB
C
/*
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* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/bitops.h>
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#include <linux/compat.h>
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#include <common.h>
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#include <command.h>
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#include <miiphy.h>
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#include <phy.h>
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#include <asm/io.h>
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#include <errno.h>
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#include "ipq_mdio.h"
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#ifdef DEBUG
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#define pr_debug(fmt, args...) printf(fmt, ##args);
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#else
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#define pr_debug(fmt, args...)
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#endif
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struct ipq_mdio_data {
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struct mii_bus *bus;
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int phy_irq[PHY_MAX_ADDR];
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};
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static int ipq_mdio_wait_busy(void)
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{
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int i;
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u32 busy;
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for (i = 0; i < IPQ_MDIO_RETRY; i++) {
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busy = readl(IPQ_MDIO_BASE +
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MDIO_CTRL_4_REG) &
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MDIO_CTRL_4_ACCESS_BUSY;
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if (!busy)
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return 0;
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}
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printf("%s: MDIO operation timed out\n",
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__func__);
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return -ETIMEDOUT;
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}
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int ipq_mdio_write(int mii_id, int regnum, u16 value)
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{
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u32 cmd;
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if (regnum & MII_ADDR_C45) {
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unsigned int mmd = (regnum >> 16) & 0x1F;
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unsigned int reg = regnum & 0xFFFF;
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writel(CTRL_0_REG_C45_DEFAULT_VALUE,
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IPQ_MDIO_BASE + MDIO_CTRL_0_REG);
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/* Issue the phy address and reg */
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writel((mii_id << 8) | mmd,
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IPQ_MDIO_BASE + MDIO_CTRL_1_REG);
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writel(reg, IPQ_MDIO_BASE + MDIO_CTRL_2_REG);
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/* issue read command */
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cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_C45_ADDR;
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writel(cmd, IPQ_MDIO_BASE + MDIO_CTRL_4_REG);
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if (ipq_mdio_wait_busy())
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return -ETIMEDOUT;
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} else {
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writel(CTRL_0_REG_DEFAULT_VALUE,
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IPQ_MDIO_BASE + MDIO_CTRL_0_REG);
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/* Issue the phy addreass and reg */
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writel((mii_id << 8 | regnum),
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IPQ_MDIO_BASE + MDIO_CTRL_1_REG);
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}
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/* Issue a write data */
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writel(value, IPQ_MDIO_BASE + MDIO_CTRL_2_REG);
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if (regnum & MII_ADDR_C45) {
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cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_C45_WRITE ;
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} else {
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cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_WRITE ;
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}
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writel(cmd, IPQ_MDIO_BASE + MDIO_CTRL_4_REG);
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/* Wait for write complete */
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if (ipq_mdio_wait_busy())
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return -ETIMEDOUT;
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return 0;
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}
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int ipq_mdio_read(int mii_id, int regnum, ushort *data)
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{
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u32 val,cmd;
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if (regnum & MII_ADDR_C45) {
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unsigned int mmd = (regnum >> 16) & 0x1F;
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unsigned int reg = regnum & 0xFFFF;
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writel(CTRL_0_REG_C45_DEFAULT_VALUE,
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IPQ_MDIO_BASE + MDIO_CTRL_0_REG);
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/* Issue the phy address and reg */
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writel((mii_id << 8) | mmd,
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IPQ_MDIO_BASE + MDIO_CTRL_1_REG);
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writel(reg, IPQ_MDIO_BASE + MDIO_CTRL_2_REG);
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/* issue read command */
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cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_C45_ADDR;
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} else {
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writel(CTRL_0_REG_DEFAULT_VALUE,
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IPQ_MDIO_BASE + MDIO_CTRL_0_REG);
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/* Issue the phy address and reg */
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writel((mii_id << 8 | regnum ) ,
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IPQ_MDIO_BASE + MDIO_CTRL_1_REG);
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/* issue read command */
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cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_READ ;
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}
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/* issue read command */
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writel(cmd, IPQ_MDIO_BASE + MDIO_CTRL_4_REG);
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if (ipq_mdio_wait_busy())
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return -ETIMEDOUT;
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if (regnum & MII_ADDR_C45) {
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cmd = MDIO_CTRL_4_ACCESS_START | MDIO_CTRL_4_ACCESS_CODE_C45_READ;
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writel(cmd, IPQ_MDIO_BASE + MDIO_CTRL_4_REG);
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if (ipq_mdio_wait_busy())
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return -ETIMEDOUT;
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}
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/* Read data */
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val = readl(IPQ_MDIO_BASE + MDIO_CTRL_3_REG);
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if (data != NULL)
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*data = val;
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return val;
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}
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int ipq_phy_write(struct mii_dev *bus,
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int addr, int dev_addr,
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int regnum, ushort value)
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{
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return ipq_mdio_write(addr, regnum, value);
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}
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int ipq_phy_read(struct mii_dev *bus,
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int addr, int dev_addr, int regnum)
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{
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return ipq_mdio_read(addr, regnum, NULL);
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}
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#ifdef CONFIG_QCA8084_PHY
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static inline void split_addr(uint32_t regaddr, uint16_t *r1, uint16_t *r2,
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uint16_t *page, uint16_t *switch_phy_id)
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{
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*r1 = regaddr & 0x1c;
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regaddr >>= 5;
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*r2 = regaddr & 0x7;
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regaddr >>= 3;
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*page = regaddr & 0xffff;
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regaddr >>= 16;
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*switch_phy_id = regaddr & 0xff;
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}
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uint32_t ipq_mii_read(uint32_t reg)
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{
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uint16_t r1, r2, page, switch_phy_id;
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uint16_t lo, hi;
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split_addr((uint32_t) reg, &r1, &r2, &page, &switch_phy_id);
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mutex_lock(&switch_mdio_lock);
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ipq_mdio_write(0x18 | (switch_phy_id >> 5), switch_phy_id & 0x1f, page);
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udelay(100);
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lo = ipq_mdio_read(0x10 | r2, r1, NULL);
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hi = ipq_mdio_read(0x10 | r2, r1 + 2, NULL);
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mutex_unlock(&switch_mdio_lock);
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return (hi << 16) | lo;
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}
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void ipq_mii_write(uint32_t reg, uint32_t val)
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{
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uint16_t r1, r2, page, switch_phy_id;
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uint16_t lo, hi;
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split_addr((uint32_t) reg, &r1, &r2, &page, &switch_phy_id);
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lo = val & 0xffff;
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hi = (uint16_t) (val >> 16);
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mutex_lock(&switch_mdio_lock);
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ipq_mdio_write(0x18 | (switch_phy_id >> 5), switch_phy_id & 0x1f, page);
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udelay(100);
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ipq_mdio_write(0x10 | r2, r1, lo);
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ipq_mdio_write(0x10 | r2, r1 + 2, hi);
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mutex_unlock(&switch_mdio_lock);
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}
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void ipq_mii_update(uint32_t reg, uint32_t mask, uint32_t val)
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{
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uint32_t new_val = 0, org_val = 0;
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org_val = ipq_mii_read(reg);
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new_val = org_val & ~mask;
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new_val |= val & mask;
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if (new_val != org_val)
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ipq_mii_write(reg, new_val);
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}
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static inline void ipq_clk_enable(uint32_t reg)
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{
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u32 val;
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val = ipq_mii_read(reg);
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val |= BIT(0);
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ipq_mii_write(reg, val);
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}
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static inline void ipq_clk_disable(uint32_t reg)
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{
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u32 val;
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val = ipq_mii_read(reg);
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val &= ~BIT(0);
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ipq_mii_write(reg, val);
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}
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static inline void ipq_clk_reset(uint32_t reg)
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{
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u32 val;
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val = ipq_mii_read(reg);
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val |= BIT(2);
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ipq_mii_write(reg, val);
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udelay(21000);
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val &= ~BIT(2);
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ipq_mii_write(reg, val);
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}
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void ipq_clock_init(void)
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{
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u32 val = 0;
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int i;
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/* Enable serdes */
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ipq_clk_enable(SRDS0_SYS_CBCR);
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ipq_clk_enable(SRDS1_SYS_CBCR);
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/* Reset serdes */
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ipq_clk_reset(SRDS0_SYS_CBCR);
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ipq_clk_reset(SRDS1_SYS_CBCR);
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/* Disable EPHY GMII clock */
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i = 0;
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while (i < 2 * PHY_ADDR_NUM) {
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ipq_clk_disable(GEPHY0_TX_CBCR + i*0x20);
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i++;
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}
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/* Enable ephy */
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ipq_clk_enable(EPHY0_SYS_CBCR);
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ipq_clk_enable(EPHY1_SYS_CBCR);
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ipq_clk_enable(EPHY2_SYS_CBCR);
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ipq_clk_enable(EPHY3_SYS_CBCR);
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/* Reset ephy */
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ipq_clk_reset(EPHY0_SYS_CBCR);
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ipq_clk_reset(EPHY1_SYS_CBCR);
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ipq_clk_reset(EPHY2_SYS_CBCR);
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ipq_clk_reset(EPHY3_SYS_CBCR);
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/* Deassert EPHY DSP */
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val = ipq_mii_read(GCC_GEPHY_MISC);
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val &= ~GENMASK(4, 0);
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ipq_mii_write(GCC_GEPHY_MISC, val);
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/* Enable efuse loading into analog circuit */
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val = ipq_mii_read(EPHY_CFG);
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/* BIT20 for PHY0 and PHY1, BIT21 for PHY2 and PHY3 */
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val &= ~GENMASK(21, 20);
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ipq_mii_write(EPHY_CFG, val);
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udelay(11000);
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}
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void ipq_phy_addr_fixup(void)
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{
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int phy_index, addr;
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u32 val;
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unsigned long phyaddr_mask = 0;
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val = ipq_mii_read(EPHY_CFG);
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for (phy_index = 0, addr = 1; addr <= 4; phy_index++, addr++) {
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phyaddr_mask |= BIT(addr);
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addr &= GENMASK(4, 0);
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val &= ~(GENMASK(4, 0) << (phy_index * PHY_ADDR_LENGTH));
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val |= addr << (phy_index * PHY_ADDR_LENGTH);
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}
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pr_debug("programme EPHY reg 0x%x with 0x%x\n", EPHY_CFG, val);
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ipq_mii_write(EPHY_CFG, val);
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/* Programe the UNIPHY address if uniphyaddr_fixup specified.
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* the UNIPHY address will select three MDIO address from
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* unoccupied MDIO address space.
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*/
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val = ipq_mii_read(UNIPHY_CFG);
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/* For qca8386, the switch occupies the other 16 MDIO address,
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* for example, if the phy address is in the range of 0 to 15,
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* the switch will occupy the MDIO address from 16 to 31.
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*/
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phyaddr_mask |= GENMASK(31, 16);
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phy_index = 0;
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for_each_clear_bit_from(addr, &phyaddr_mask, PHY_MAX_ADDR) {
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if (phy_index >= UNIPHY_ADDR_NUM)
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break;
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val &= ~(GENMASK(4, 0) << (phy_index * PHY_ADDR_LENGTH));
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val |= addr << (phy_index * PHY_ADDR_LENGTH);
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phy_index++;
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}
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if (phy_index < UNIPHY_ADDR_NUM) {
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for_each_clear_bit(addr, &phyaddr_mask, PHY_MAX_ADDR) {
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if (phy_index >= UNIPHY_ADDR_NUM)
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break;
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val &= ~(GENMASK(4, 0) << (phy_index * PHY_ADDR_LENGTH));
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val |= addr << (phy_index * PHY_ADDR_LENGTH);
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phy_index++;
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}
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}
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pr_debug("programme UNIPHY reg 0x%x with 0x%x\n", UNIPHY_CFG, val);
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ipq_mii_write(UNIPHY_CFG, val);
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}
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#endif
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int ipq_sw_mdio_init(const char *name)
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{
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struct mii_dev *bus = mdio_alloc();
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if(!bus) {
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printf("Failed to allocate IPQ MDIO bus\n");
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return -1;
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}
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bus->read = ipq_phy_read;
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bus->write = ipq_phy_write;
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bus->reset = NULL;
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snprintf(bus->name, MDIO_NAME_LEN, name);
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return mdio_register(bus);
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}
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#ifdef CONFIG_QCA8084_PHY
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static int do_ipq_mii(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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char op[2];
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unsigned int reg = 0;
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unsigned short data = 0;
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if (argc < 2)
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return CMD_RET_USAGE;
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op[0] = argv[1][0];
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if (strlen(argv[1]) > 1)
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op[1] = argv[1][1];
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else
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op[1] = '\0';
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if (argc >= 3)
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reg = simple_strtoul(argv[2], NULL, 16);
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if (argc >= 4)
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data = simple_strtoul(argv[3], NULL, 16);
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if (op[0] == 'r') {
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data = ipq_mii_read(reg);
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printf("0x%x\n", data);
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} else if (op[0] == 'w') {
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ipq_mii_write(reg, data);
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} else {
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return CMD_RET_USAGE;
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}
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return 0;
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}
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U_BOOT_CMD(
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ipq_mii, 4, 1, do_ipq_mii,
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"IPQ mii utility commands",
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"ipq_mii read <reg> - read IPQ MII register <reg>\n"
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"ipq_mii write <reg> <data> - write IPQ MII register <reg> with <data>\n"
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);
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#endif
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static int do_ipq_mdio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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char op[2];
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unsigned int addr = 0, reg = 0;
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unsigned short data = 0;
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if (argc < 2)
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return CMD_RET_USAGE;
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op[0] = argv[1][0];
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if (strlen(argv[1]) > 1)
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op[1] = argv[1][1];
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else
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op[1] = '\0';
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if (argc >= 3)
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addr = simple_strtoul(argv[2], NULL, 16);
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if (argc >= 4)
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reg = simple_strtoul(argv[3], NULL, 16);
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if (argc >= 5)
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data = simple_strtoul(argv[4], NULL, 16);
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if (op[0] == 'r') {
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data = ipq_mdio_read(addr, reg, NULL);
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printf("0x%x\n", data);
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} else if (op[0] == 'w') {
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ipq_mdio_write(addr, reg, data);
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} else {
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return CMD_RET_USAGE;
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}
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return 0;
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}
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U_BOOT_CMD(
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ipq_mdio, 5, 1, do_ipq_mdio,
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"IPQ mdio utility commands",
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"ipq_mdio read <addr> <reg> - read IPQ MDIO PHY <addr> register <reg>\n"
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"ipq_mdio write <addr> <reg> <data> - write IPQ MDIO PHY <addr> register <reg>\n"
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"Addr and/or reg may be ranges, e.g. 0-7."
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);
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